zephyr/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33-pinctrl.dtsi

/*
 * NOTE: File generated by lpc_cfg_utils.py
 * from MIMXRT595-EVK.mex
 *
 * Copyright 2022, NXP
 * SPDX-License-Identifier: Apache-2.0
 */


#include <nxp/nxp_imx/rt/MIMXRT595SFFOC-pinctrl.h>

&pinctrl {
	pinmux_flexcomm0_usart: pinmux_flexcomm0_usart {
		group0 {
			pinmux = <FC0_RXD_SDA_MOSI_DATA_PIO0_2>;
			input-enable;
			slew-rate = "normal";
			drive-strength = "normal";
		};
		group1 {
			pinmux = <FC0_TXD_SCL_MISO_WS_PIO0_1>;
			slew-rate = "normal";
			drive-strength = "normal";
		};
	};

	pinmux_flexcomm4_i2c: pinmux_flexcomm4_i2c {
		group0 {
			pinmux = <FC4_TXD_SCL_MISO_WS_PIO0_29>,
			       <FC4_RXD_SDA_MOSI_DATA_PIO0_30>;
			input-enable;
			slew-rate = "normal";
			drive-strength = "high";
			drive-open-drain;
		};
	};

	pinmux_flexcomm12_usart: pinmux_flexcomm12_usart {
		group0 {
			pinmux = <FC12_RXD_SDA_MOSI_PIO4_31>;
			input-enable;
			slew-rate = "normal";
			drive-strength = "normal";
		};
		group1 {
			pinmux = <FC12_TXD_SCL_MISO_PIO4_30>;
			slew-rate = "normal";
			drive-strength = "normal";
		};
	};

	pinmux_flexcomm16_spi: pinmux_flexcomm16_spi {
		group0 {
			pinmux = <HS_SPI1_SCK_PIO1_3>,
					<HS_SPI1_MISO_PIO1_4>,
					<HS_SPI1_MOSI_PIO1_5>,
					<HS_SPI1_SSELN0_PIO1_6>;
			input-enable;
			slew-rate = "normal";
			drive-strength = "normal";
		};
	};

	pinmux_pmic_i2c: pinmux_pmic_i2c {
		group0 {
			pinmux = <PMIC_I2C_SCL>,
				<PMIC_I2C_SDA>;
			bias-pull-up;
			input-enable;
			slew-rate = "normal";
			drive-strength = "normal";
			drive-open-drain;
		};
	};

};