130 lines
3.6 KiB
C
130 lines
3.6 KiB
C
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/* dw_spi_priv.h - Designware SPI driver private definitions */
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __DW_SPI_PRIV_H__
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#define __DW_SPI_PRIV_H__
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#include <spi.h>
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typedef void (*spi_dw_config_t)(struct device *dev);
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/* Private structures */
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struct spi_dw_config {
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uint32_t regs;
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uint32_t irq;
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uint32_t int_mask;
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#ifdef CONFIG_SPI_DW_CLOCK_GATE
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void *clock_data;
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#endif /* CONFIG_SPI_DW_CLOCK_GATE */
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spi_dw_config_t config_func;
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};
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struct spi_dw_data {
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#ifdef CONFIG_SPI_DW_CLOCK_GATE
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struct device *clock;
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#endif /* CONFIG_SPI_DW_CLOCK_GATE */
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uint32_t slave;
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spi_callback callback;
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void *user_data;
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uint8_t *tx_buf;
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uint32_t tx_buf_len;
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uint8_t *rx_buf;
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uint32_t rx_buf_len;
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uint32_t t_len;
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};
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/* Registers */
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#define DW_SPI_REG_CTRLR0 (0x00)
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#define DW_SPI_REG_CTRLR1 (0x04)
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#define DW_SPI_REG_SSIENR (0x08)
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#define DW_SPI_REG_MWCR (0x0c)
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#define DW_SPI_REG_SER (0x10)
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#define DW_SPI_REG_BAUDR (0x14)
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#define DW_SPI_REG_TXFTLR (0x18)
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#define DW_SPI_REG_RXFTLR (0x1c)
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#define DW_SPI_REG_TXFLR (0x20)
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#define DW_SPI_REG_RXFLR (0x24)
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#define DW_SPI_REG_SR (0x28)
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#define DW_SPI_REG_IMR (0x2c)
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#define DW_SPI_REG_ISR (0x30)
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#define DW_SPI_REG_RISR (0x34)
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#define DW_SPI_REG_TXOICR (0x38)
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#define DW_SPI_REG_RXOICR (0x3c)
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#define DW_SPI_REG_RXUICR (0x40)
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#define DW_SPI_REG_MSTICR (0x44)
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#define DW_SPI_REG_ICR (0x48)
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#define DW_SPI_REG_DMACR (0x4c)
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#define DW_SPI_REG_DMATDLR (0x50)
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#define DW_SPI_REG_DMARDLR (0x54)
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#define DW_SPI_REG_IDR (0x58)
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#define DW_SPI_REG_SSI_COMP_VERSION (0x5c)
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#define DW_SPI_REG_DR (0x60)
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#define DW_SPI_REG_RX_SAMPLE_DLY (0xf0)
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#define DW_SSI_COMP_VERSION (0x3332332a)
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/* CTRLR0 settings */
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#define DW_SPI_CTRLR0_SCPH (0x1 << 6)
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#define DW_SPI_CTRLR0_SCPOL (0x1 << 7)
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#define DW_SPI_CTRLR0_SRL (0x1 << 11)
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#define DW_SPI_CTRLR0_DFS(__bpw) (((__bpw) - 1) << 16)
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/* SSIENR bits */
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#define DW_SPI_SSIENR_SSIEN_BIT (0)
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/* SR bits and values */
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#define DW_SPI_SR_BUSY_BIT (0)
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#define DW_SPI_SR_TFNF_BIT (1)
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#define DW_SPI_SR_RFNE_BIT (3)
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/* IMR values */
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#define DW_SPI_IMR_TXEIM_BIT (0)
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#define DW_SPI_IMR_TXOIM_BIT (1)
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#define DW_SPI_IMR_RXUIM_BIT (2)
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#define DW_SPI_IMR_RXOIM_BIT (3)
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#define DW_SPI_IMR_RXFIM_BIT (4)
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#define DW_SPI_IMR_MSTIM_BIT (5)
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/* ISR values */
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#define DW_SPI_ISR_TXEIS (0x1 << DW_SPI_IMR_TXEIM_BIT)
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#define DW_SPI_ISR_TXOIF (0x1 << DW_SPI_IMR_TXOIM_BIT)
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#define DW_SPI_ISR_RXUIS (0x1 << DW_SPI_IMR_RXUIM_BIT)
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#define DW_SPI_ISR_RXOIS (0x1 << DW_SPI_IMR_RXOIM_BIT)
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#define DW_SPI_ISR_RXFIS (0x1 << DW_SPI_IMR_RXFIM_BIT)
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#define DW_SPI_ISR_MSTIS (0x1 << DW_SPI_IMR_MSTIM_BIT)
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/* Error interrupt */
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#define DW_SPI_ISR_ERRORS_MASK (DW_SPI_ISR_TXOIF | \
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DW_SPI_ISR_RXUIS | \
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DW_SPI_ISR_RXOIS | \
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DW_SPI_ISR_MSTIS)
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/* ICR Bit */
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#define DW_SPI_SR_ICR_BIT (0)
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/* Threshold defaults */
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#define DW_SPI_TXFTLR_DFLT (8)
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#define DW_SPI_RXFTLR_DFLT (8)
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/* Interrupt mask (IMR) */
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#define DW_SPI_IMR_MASK (0x0)
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#define DW_SPI_IMR_UNMASK (0x1f)
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#define DW_SPI_IMR_MASK_TX (~(0x3))
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#define DW_SPI_IMR_MASK_RX (~(0x28))
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#endif /* __DW_SPI_PRIV_H__ */
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