2021-08-18 17:18:44 +08:00
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/*
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* Copyright (c) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_PCIE_HOST_PTM_H_
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#define ZEPHYR_DRIVERS_PCIE_HOST_PTM_H_
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2022-05-06 16:25:46 +08:00
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#include <zephyr/drivers/pcie/pcie.h>
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#include <zephyr/drivers/pcie/cap.h>
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2021-08-18 17:18:44 +08:00
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#define PTM_CAP_REG_OFFSET 0x04U
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union ptm_cap_reg {
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struct {
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uint32_t requester : 1;
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uint32_t responder : 1;
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uint32_t root : 1;
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uint32_t _reserved1 : 5;
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uint32_t local_clock_granularity : 8;
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uint32_t _reserved2 : 16;
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};
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uint32_t raw;
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};
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#define PTM_CTRL_REG_OFFSET 0x08U
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union ptm_ctrl_reg {
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struct {
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uint32_t ptm_enable : 1;
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uint32_t root_select : 1;
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uint32_t _reserved1 : 6;
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uint32_t effective_granularity : 8;
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uint32_t _reserved2 : 16;
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};
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uint32_t raw;
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};
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struct pcie_ptm_root_config {
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2022-11-11 18:20:23 +08:00
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struct pcie_dev *pcie;
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2021-08-18 17:18:44 +08:00
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};
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#endif /* ZEPHYR_DRIVERS_PCIE_HOST_PTM_H_ */
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