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zephyr/boards/xtensa/esp32/esp32_defconfig

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license: cleanup: add SPDX Apache-2.0 license identifier Update the files which contain no license information with the 'Apache-2.0' SPDX license identifier. Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of Zephyr, which is Apache version 2. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-06 21:08:09 +08:00
# SPDX-License-Identifier: Apache-2.0
boards: xtensa: Add ESP32 board This is based on the work of Rajavardhan Gundi. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-05-04 05:29:36 +08:00
CONFIG_XTENSA_RESET_VECTOR=n
CONFIG_BOARD_ESP32=y
CONFIG_SOC_ESP32=y
CONFIG_MAIN_STACK_SIZE=2048
drivers: esp32/clock_control: support UART, I2C - Change default CPU Clock to 240MHz (PLL is activated) - I2C, UART will use sysclk from clock driver - esp32_enable_peripheral replaced by clock_control_on Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
2020-05-29 03:01:49 +08:00
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
drivers: esp32: Add minimal UART driver based on ROM routines This is a minimal driver enabling console output during the port bringup. While the driver works, only one of the three UART devices are supported, and there isn't any way to change any parameters or use interrupts. This will most likely be superceded by a proper driver after the port has matured. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-05-11 08:12:12 +08:00
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_ESP32=y
soc: esp32: Define __start as a C function The first stage bootloader, part of the ESP32 ROM, already sets up a stack that's sufficient to execute C programs. So, instead of implementing __stack() in assembly, do it in C to simplify things slightly. This ESP32-specific initialization will perform the following: - Disable the watchdog timer that's enabled by the bootloader - Move exception handlers to IRAM - Disable normal interrupts - Disable the second CPU - Zero out the BSS segment Things that might be performed in the future include setting up the CPU frequency, memory protection regions, and enabling the flash cache. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-14 01:48:38 +08:00
CONFIG_XTENSA_USE_CORE_CRT1=n
drivers: pinmux: Add pin multiplexer driver for ESP32 This implements a driver for the pin multiplexer as present in the ESP32 SoCs. All APIs are supported. Jira: ZEP-2297 Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-27 08:07:43 +08:00
CONFIG_PINMUX=y
CONFIG_PINMUX_ESP32=y
drivers: gpio: esp32: Add ESP32 GPIO driver This provides basic GPIO support, with interrupts, and the ability to read and write to ports on a pin-by-pin basis. Jira: ZEP-2286 Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-20 07:58:29 +08:00
CONFIG_GPIO=y
CONFIG_GPIO_ESP32=y
drivers: random: Add ESP32 random number generator driver The random number generator from ESP32 uses noise from Wi-Fi and Bluetooth radios. If these are off, a pseudo-random number is generated instead; this is currently the case, but even though it's a black box, it's arguably better than returning a timestamp as a pseudo-random number generator. According to the ESP32 Technical Reference manual, the RNG passed the Dieharder Random Number Test suite (version 3.31.1)[1], but nothing has been said about the quality of the PRNG. The RNG register is read directly; no effort is made to use its contents to feed an entropy pool in a way that's similar to /dev/random on POSIX systems, as no such subsystem exists on Zephyr at the moment. [1] http://webhome.phy.duke.edu/~rgb/General/dieharder.php Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-07-01 01:12:07 +08:00
arch: xtensa: Convert Xtensa port to use gen_isr_table The Xtensa port was the only one remaining to be converted to the new way of connecting interrupts in Zephyr. Some things are still unconverted, mainly the exception table, and this will be performed another time. Of note: _irq_priority_set() isn't called on _ARCH_IRQ_CONNECT(), since IRQs can't change priority on Xtensa: while the architecture has the concept of interrupt priority levels, each line has a fixed level and can't be changed. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-07-08 01:35:18 +08:00
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
drivers: esp32: I2C driver implementation Supports both master and slave mode, standard and fast modes, configurable timeouts, and a few other tunable settings. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-24 08:24:40 +08:00
CONFIG_I2C=y
CONFIG_I2C_ESP32=y
CONFIG_I2C_0=y
CONFIG_I2C_1=y
CONFIG_I2C_2=n
CONFIG_I2C_3=n
drivers: esp32/clock_control: Add Clock Driver - Support PLL for Higher Frequencies 80,160,240 MHz - Support XTAL Frequencies 26MHz, 40MHz - Clock Driver can't be disabled, because all of the other drivers will depend on it to get their operating Frequency based on chosen clock source (XTAL/PLL). - Add needed references to BBPLL i2c bus ROM functions. - Add `rtc` node to Device Tree. - Since All Peripherals Frequency is depending on CPU_CLK Source, `clock-source` property added to CPU node Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
2020-05-23 21:46:29 +08:00
CONFIG_CLOCK_CONTROL=y