96 lines
1.8 KiB
Plaintext
96 lines
1.8 KiB
Plaintext
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/*
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* Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <mem.h>
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#include <arm64/armv8-r.dtsi>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "FVP BaseR AEMv8R";
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chosen {
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/*
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* The SRAM node is actually located in the
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* DRAM region of the FVP BaseR AEMv8R.
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*/
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zephyr,sram = &dram0;
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zephyr,flash = &flash0;
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r82";
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reg = <0>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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label = "arch_timer";
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};
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uartclk: apb-pclk {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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soc {
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interrupt-parent = <&gic>;
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gic: interrupt-controller@af000000 {
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compatible = "arm,gic";
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reg = <0xaf000000 0x1000>,
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<0xaf100000 0x100>;
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interrupt-controller;
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#interrupt-cells = <4>;
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label = "GIC";
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status = "okay";
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};
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uart0: uart@9c090000 {
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compatible = "arm,pl011";
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reg = <0x9c090000 0x1000>;
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status = "disabled";
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interrupts = <GIC_SPI 1 0 IRQ_TYPE_LEVEL>;
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interrupt-names = "irq_0";
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label = "UART_0";
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clocks = <&uartclk>;
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};
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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dram0: memory@10000000 {
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compatible = "mmio-dram";
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reg = <0x10000000 DT_SIZE_K(2048)>;
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};
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};
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};
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&uart0 {
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status = "okay";
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current-speed = <115200>;
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};
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