2016-01-14 21:48:12 +08:00
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/* spi_dw.c - Designware SPI driver implementation */
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2015-11-22 10:28:21 +08:00
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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2016-03-10 01:38:02 +08:00
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#include <errno.h>
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2015-11-22 10:28:21 +08:00
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#include <nanokernel.h>
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#include <arch/cpu.h>
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#include <misc/__assert.h>
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#include <board.h>
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#include <device.h>
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#include <init.h>
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#include <sys_io.h>
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#include <clock_control.h>
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#include <misc/util.h>
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#include <spi.h>
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2016-01-14 21:48:12 +08:00
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#include <spi_dw.h>
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2015-11-22 10:28:21 +08:00
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2015-12-11 01:52:56 +08:00
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#ifdef CONFIG_IOAPIC
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#include <drivers/ioapic.h>
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#endif
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2016-05-08 07:15:28 +08:00
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#define SYS_LOG_DOMAIN "SPI DW"
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_SPI_LEVEL
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#include <misc/sys_log.h>
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#if (CONFIG_SYS_LOG_SPI_LEVEL == 4)
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2016-02-05 00:02:03 +08:00
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#define DBG_COUNTER_INIT() \
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uint32_t __cnt = 0
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#define DBG_COUNTER_INC() \
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(__cnt++)
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#define DBG_COUNTER_RESULT() \
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(__cnt)
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2015-11-22 10:28:21 +08:00
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#else
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2016-05-08 07:15:28 +08:00
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#define DBG_COUNTER_INIT() {; }
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#define DBG_COUNTER_INC() {; }
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2016-05-16 02:11:16 +08:00
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#define DBG_COUNTER_RESULT() 0
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2016-05-08 07:15:28 +08:00
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#endif
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2015-11-22 10:28:21 +08:00
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spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 02:55:09 +08:00
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#ifdef SPI_DW_SPI_CLOCK
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#define SPI_DW_CLK_DIVIDER(ssi_clk_hz) \
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((SPI_DW_SPI_CLOCK / ssi_clk_hz) & 0xFFFF)
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/* provision for soc.h providing a clock that is different than CPU clock */
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#else
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2016-04-01 14:41:30 +08:00
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#define SPI_DW_CLK_DIVIDER(ssi_clk_hz) \
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((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / ssi_clk_hz) & 0xFFFF)
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spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 02:55:09 +08:00
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#endif
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2016-04-01 14:41:30 +08:00
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2015-11-22 10:28:21 +08:00
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static void completed(struct device *dev, int error)
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{
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struct spi_dw_config *info = dev->config->config_info;
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struct spi_dw_data *spi = dev->driver_data;
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2016-02-04 20:57:52 +08:00
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if (error) {
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goto out;
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2016-01-15 17:11:24 +08:00
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}
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spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 02:55:09 +08:00
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/*
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* There are several situations here.
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* 1. spi_write w rx_buf - need last_tx && rx_buf_len zero to be done.
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* 2. spi_write w/o rx_buf - only need to determine when write is done.
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* 3. spi_read - need rx_buf_len zero.
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*/
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if (spi->tx_buf && spi->rx_buf) {
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if (!spi->last_tx || spi->rx_buf_len)
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return;
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} else if (spi->tx_buf) {
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if (!spi->last_tx)
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return;
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} else { /* or, spi->rx_buf!=0 */
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if (spi->rx_buf_len)
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return;
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2015-11-22 10:28:21 +08:00
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}
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2016-02-04 20:57:52 +08:00
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out:
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spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 02:55:09 +08:00
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/* need to give time for FIFOs to drain before issuing more commands */
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while (test_bit_sr_busy(info->regs)) {
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}
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2015-12-08 20:30:41 +08:00
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spi->error = error;
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2015-11-22 10:28:21 +08:00
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/* Disabling interrupts */
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write_imr(DW_SPI_IMR_MASK, info->regs);
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2016-01-19 00:27:21 +08:00
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/* Disabling the controller */
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clear_bit_ssienr(info->regs);
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2015-11-22 10:28:21 +08:00
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2016-01-19 00:16:24 +08:00
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_spi_control_cs(dev, 0);
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2016-02-05 00:02:03 +08:00
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2016-05-08 07:15:28 +08:00
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SYS_LOG_DBG("SPI transaction completed %s error",
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2016-02-05 00:02:03 +08:00
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error ? "with" : "without");
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2016-01-27 04:38:44 +08:00
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device_sync_call_complete(&spi->sync);
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2015-11-22 10:28:21 +08:00
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}
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static void push_data(struct device *dev)
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{
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struct spi_dw_config *info = dev->config->config_info;
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struct spi_dw_data *spi = dev->driver_data;
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2015-12-19 07:26:42 +08:00
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uint32_t data = 0;
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2016-01-15 17:11:24 +08:00
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uint32_t f_tx;
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2016-02-05 00:02:03 +08:00
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DBG_COUNTER_INIT();
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2015-11-22 10:28:21 +08:00
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spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 02:55:09 +08:00
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if (spi->rx_buf) {
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f_tx = DW_SPI_FIFO_DEPTH - read_txflr(info->regs) -
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read_rxflr(info->regs);
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if ((int)f_tx < 0) {
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f_tx = 0; /* if rx-fifo is full, hold off tx */
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}
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} else {
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f_tx = DW_SPI_FIFO_DEPTH - read_txflr(info->regs);
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}
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if (f_tx && (spi->tx_buf_len == 0)) {
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/* room in fifo, yet nothing to send */
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spi->last_tx = 1; /* setting last_tx indicates TX is done */
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}
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2016-01-15 17:11:24 +08:00
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while (f_tx) {
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2015-11-22 10:28:21 +08:00
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if (spi->tx_buf && spi->tx_buf_len > 0) {
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2015-12-19 07:26:42 +08:00
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switch (spi->dfs) {
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case 1:
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2016-03-04 18:54:09 +08:00
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data = UNALIGNED_GET((uint8_t *)(spi->tx_buf));
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2015-12-19 07:26:42 +08:00
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break;
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case 2:
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2016-03-04 18:54:09 +08:00
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data = UNALIGNED_GET((uint16_t *)(spi->tx_buf));
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2015-12-19 07:26:42 +08:00
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break;
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#ifndef CONFIG_ARC
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case 4:
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2016-03-04 18:54:09 +08:00
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data = UNALIGNED_GET((uint32_t *)(spi->tx_buf));
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2015-12-19 07:26:42 +08:00
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break;
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#endif
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}
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spi->tx_buf += spi->dfs;
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2016-01-15 17:11:24 +08:00
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spi->tx_buf_len--;
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2015-11-22 10:28:21 +08:00
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} else if (spi->rx_buf && spi->rx_buf_len > 0) {
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/* No need to push more than necessary */
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2016-01-15 17:11:24 +08:00
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if (spi->rx_buf_len - spi->fifo_diff <= 0) {
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2015-11-22 10:28:21 +08:00
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break;
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}
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data = 0;
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} else {
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/* Nothing to push anymore */
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break;
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}
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write_dr(data, info->regs);
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2016-01-15 17:11:24 +08:00
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f_tx--;
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spi->fifo_diff++;
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2016-02-05 00:02:03 +08:00
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DBG_COUNTER_INC();
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2015-11-22 10:28:21 +08:00
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}
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spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 02:55:09 +08:00
|
|
|
if (spi->last_tx) {
|
2016-01-25 17:01:50 +08:00
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|
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write_txftlr(0, info->regs);
|
spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 02:55:09 +08:00
|
|
|
/* prevents any further interrupts demanding TX fifo fill */
|
2016-01-25 17:01:50 +08:00
|
|
|
}
|
|
|
|
|
|
2016-05-08 07:15:28 +08:00
|
|
|
SYS_LOG_DBG("Pushed: %d", DBG_COUNTER_RESULT());
|
2015-11-22 10:28:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void pull_data(struct device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct spi_dw_config *info = dev->config->config_info;
|
|
|
|
|
struct spi_dw_data *spi = dev->driver_data;
|
2015-12-19 07:26:42 +08:00
|
|
|
uint32_t data = 0;
|
2016-02-05 00:02:03 +08:00
|
|
|
DBG_COUNTER_INIT();
|
2015-11-22 10:28:21 +08:00
|
|
|
|
2016-01-15 17:11:24 +08:00
|
|
|
while (read_rxflr(info->regs)) {
|
2015-11-22 10:28:21 +08:00
|
|
|
data = read_dr(info->regs);
|
2016-02-05 00:02:03 +08:00
|
|
|
DBG_COUNTER_INC();
|
2015-11-22 10:28:21 +08:00
|
|
|
|
|
|
|
|
if (spi->rx_buf && spi->rx_buf_len > 0) {
|
2015-12-19 07:26:42 +08:00
|
|
|
switch (spi->dfs) {
|
|
|
|
|
case 1:
|
2016-03-04 18:54:09 +08:00
|
|
|
UNALIGNED_PUT(data, (uint8_t *)spi->rx_buf);
|
2015-12-19 07:26:42 +08:00
|
|
|
break;
|
|
|
|
|
case 2:
|
2016-03-04 18:54:09 +08:00
|
|
|
UNALIGNED_PUT(data, (uint16_t *)spi->rx_buf);
|
2015-12-19 07:26:42 +08:00
|
|
|
break;
|
|
|
|
|
#ifndef CONFIG_ARC
|
|
|
|
|
case 4:
|
2016-03-04 18:54:09 +08:00
|
|
|
UNALIGNED_PUT(data, (uint32_t *)spi->rx_buf);
|
2015-12-19 07:26:42 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
spi->rx_buf += spi->dfs;
|
2016-01-15 17:11:24 +08:00
|
|
|
spi->rx_buf_len--;
|
2015-11-22 10:28:21 +08:00
|
|
|
}
|
2016-01-15 17:11:24 +08:00
|
|
|
|
|
|
|
|
spi->fifo_diff--;
|
|
|
|
|
}
|
|
|
|
|
|
2016-01-25 17:01:50 +08:00
|
|
|
if (!spi->rx_buf_len && spi->tx_buf_len < DW_SPI_FIFO_DEPTH) {
|
|
|
|
|
write_rxftlr(spi->tx_buf_len - 1, info->regs);
|
2016-01-15 17:11:24 +08:00
|
|
|
} else if (read_rxftlr(info->regs) >= spi->rx_buf_len) {
|
|
|
|
|
write_rxftlr(spi->rx_buf_len - 1, info->regs);
|
2015-11-22 10:28:21 +08:00
|
|
|
}
|
|
|
|
|
|
2016-05-08 07:15:28 +08:00
|
|
|
SYS_LOG_DBG("Pulled: %d", DBG_COUNTER_RESULT());
|
2015-11-22 10:28:21 +08:00
|
|
|
}
|
|
|
|
|
|
2016-01-19 00:27:21 +08:00
|
|
|
static inline bool _spi_dw_is_controller_ready(struct device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct spi_dw_config *info = dev->config->config_info;
|
|
|
|
|
|
|
|
|
|
if (test_bit_ssienr(info->regs) || test_bit_sr_busy(info->regs)) {
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2015-11-22 10:28:21 +08:00
|
|
|
static int spi_dw_configure(struct device *dev,
|
2015-12-08 20:30:41 +08:00
|
|
|
struct spi_config *config)
|
2015-11-22 10:28:21 +08:00
|
|
|
{
|
|
|
|
|
struct spi_dw_config *info = dev->config->config_info;
|
|
|
|
|
struct spi_dw_data *spi = dev->driver_data;
|
|
|
|
|
uint32_t flags = config->config;
|
|
|
|
|
uint32_t ctrlr0 = 0;
|
|
|
|
|
uint32_t mode;
|
|
|
|
|
|
2016-05-08 07:15:28 +08:00
|
|
|
SYS_LOG_DBG("%s: %p (0x%x), %p", __func__, dev, info->regs, config);
|
2015-11-22 10:28:21 +08:00
|
|
|
|
|
|
|
|
/* Check status */
|
2016-01-19 00:27:21 +08:00
|
|
|
if (!_spi_dw_is_controller_ready(dev)) {
|
2016-05-08 07:15:28 +08:00
|
|
|
SYS_LOG_DBG("%s: Controller is busy", __func__);
|
2016-03-10 02:26:12 +08:00
|
|
|
return -EBUSY;
|
2015-11-22 10:28:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Word size */
|
|
|
|
|
ctrlr0 |= DW_SPI_CTRLR0_DFS(SPI_WORD_SIZE_GET(flags));
|
|
|
|
|
|
2015-12-19 07:26:42 +08:00
|
|
|
/* Determine how many bytes are required per-frame */
|
|
|
|
|
spi->dfs = SPI_DFS_TO_BYTES(SPI_WORD_SIZE_GET(flags));
|
|
|
|
|
|
2015-11-22 10:28:21 +08:00
|
|
|
/* SPI mode */
|
|
|
|
|
mode = SPI_MODE(flags);
|
|
|
|
|
if (mode & SPI_MODE_CPOL) {
|
|
|
|
|
ctrlr0 |= DW_SPI_CTRLR0_SCPOL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mode & SPI_MODE_CPHA) {
|
|
|
|
|
ctrlr0 |= DW_SPI_CTRLR0_SCPH;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mode & SPI_MODE_LOOP) {
|
|
|
|
|
ctrlr0 |= DW_SPI_CTRLR0_SRL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Installing the configuration */
|
|
|
|
|
write_ctrlr0(ctrlr0, info->regs);
|
|
|
|
|
|
2016-04-01 14:41:30 +08:00
|
|
|
/*
|
|
|
|
|
* Configure the rate. Use this small hack to allow the user to call
|
|
|
|
|
* spi_configure() with both a divider (as the driver was initially
|
|
|
|
|
* written) and a frequency (as the SPI API suggests to). The clock
|
|
|
|
|
* divider is a 16bit value, hence we can fairly, and safely, assume
|
|
|
|
|
* that everything above this value is a frequency. The trade-off is
|
|
|
|
|
* that if one wants to use a bus frequency of 64kHz (or less), it has
|
|
|
|
|
* the use a divider...
|
|
|
|
|
*/
|
|
|
|
|
if (config->max_sys_freq > 0xffff) {
|
|
|
|
|
write_baudr(SPI_DW_CLK_DIVIDER(config->max_sys_freq),
|
|
|
|
|
info->regs);
|
|
|
|
|
} else {
|
|
|
|
|
write_baudr(config->max_sys_freq, info->regs);
|
|
|
|
|
}
|
2015-11-22 10:28:21 +08:00
|
|
|
|
2016-03-10 01:01:20 +08:00
|
|
|
return 0;
|
2015-11-22 10:28:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int spi_dw_slave_select(struct device *dev, uint32_t slave)
|
|
|
|
|
{
|
|
|
|
|
struct spi_dw_data *spi = dev->driver_data;
|
|
|
|
|
|
2016-05-08 07:15:28 +08:00
|
|
|
SYS_LOG_DBG("%s: %p %d", __func__, dev, slave);
|
2016-02-05 00:02:03 +08:00
|
|
|
|
2016-05-16 02:11:16 +08:00
|
|
|
if (slave == 0 || slave > 16) {
|
2016-03-10 02:22:04 +08:00
|
|
|
return -EINVAL;
|
2015-11-22 10:28:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
spi->slave = 1 << (slave - 1);
|
|
|
|
|
|
2016-03-10 01:01:20 +08:00
|
|
|
return 0;
|
2015-11-22 10:28:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int spi_dw_transceive(struct device *dev,
|
2016-03-04 15:07:53 +08:00
|
|
|
const void *tx_buf, uint32_t tx_buf_len,
|
|
|
|
|
void *rx_buf, uint32_t rx_buf_len)
|
2015-11-22 10:28:21 +08:00
|
|
|
{
|
|
|
|
|
struct spi_dw_config *info = dev->config->config_info;
|
|
|
|
|
struct spi_dw_data *spi = dev->driver_data;
|
2016-01-15 17:11:24 +08:00
|
|
|
uint32_t rx_thsld = DW_SPI_RXFTLR_DFLT;
|
spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 02:55:09 +08:00
|
|
|
uint32_t imask;
|
2015-11-22 10:28:21 +08:00
|
|
|
|
2016-05-08 07:15:28 +08:00
|
|
|
SYS_LOG_DBG("%s: %p, %p, %u, %p, %u",
|
2016-02-05 00:02:03 +08:00
|
|
|
__func__, dev, tx_buf, tx_buf_len, rx_buf, rx_buf_len);
|
2015-11-22 10:28:21 +08:00
|
|
|
|
|
|
|
|
/* Check status */
|
2016-01-19 00:27:21 +08:00
|
|
|
if (!_spi_dw_is_controller_ready(dev)) {
|
2016-05-08 07:15:28 +08:00
|
|
|
SYS_LOG_DBG("%s: Controller is busy", __func__);
|
2016-03-10 02:26:12 +08:00
|
|
|
return -EBUSY;
|
2015-11-22 10:28:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Set buffers info */
|
|
|
|
|
spi->tx_buf = tx_buf;
|
2016-01-15 17:11:24 +08:00
|
|
|
spi->tx_buf_len = tx_buf_len/spi->dfs;
|
2015-11-22 10:28:21 +08:00
|
|
|
spi->rx_buf = rx_buf;
|
spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 02:55:09 +08:00
|
|
|
if (rx_buf) {
|
|
|
|
|
spi->rx_buf_len = rx_buf_len/spi->dfs;
|
|
|
|
|
} else {
|
|
|
|
|
spi->rx_buf_len = 0; /* must be zero if no buffer */
|
|
|
|
|
}
|
2016-01-15 17:11:24 +08:00
|
|
|
spi->fifo_diff = 0;
|
spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 02:55:09 +08:00
|
|
|
spi->last_tx = 0;
|
2016-01-15 17:11:24 +08:00
|
|
|
|
spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 02:55:09 +08:00
|
|
|
/* Tx Threshold */
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
write_txftlr(DW_SPI_TXFTLR_DFLT, info->regs);
|
|
|
|
|
|
2016-01-15 17:11:24 +08:00
|
|
|
/* Does Rx thresholds needs to be lower? */
|
spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 02:55:09 +08:00
|
|
|
if (spi->rx_buf_len && spi->rx_buf_len < DW_SPI_FIFO_DEPTH) {
|
2016-01-15 17:11:24 +08:00
|
|
|
rx_thsld = spi->rx_buf_len - 1;
|
spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 02:55:09 +08:00
|
|
|
} else if (!spi->rx_buf_len && spi->tx_buf_len < DW_SPI_FIFO_DEPTH) {
|
2016-01-15 17:11:24 +08:00
|
|
|
rx_thsld = spi->tx_buf_len - 1;
|
spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 02:55:09 +08:00
|
|
|
/* TODO: why? */
|
2016-01-15 17:11:24 +08:00
|
|
|
}
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
|
2016-01-15 17:11:24 +08:00
|
|
|
write_rxftlr(rx_thsld, info->regs);
|
2015-11-22 10:28:21 +08:00
|
|
|
|
|
|
|
|
/* Slave select */
|
|
|
|
|
write_ser(spi->slave, info->regs);
|
|
|
|
|
|
2016-01-19 00:16:24 +08:00
|
|
|
_spi_control_cs(dev, 1);
|
|
|
|
|
|
2015-11-22 10:28:21 +08:00
|
|
|
/* Enable interrupts */
|
spi: Stability improvements to the DesignWare SPI driver
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 02:55:09 +08:00
|
|
|
imask = DW_SPI_IMR_UNMASK;
|
|
|
|
|
if (!rx_buf) {
|
|
|
|
|
/* if there is no rx buffer, keep all rx interrupts masked */
|
|
|
|
|
imask &= DW_SPI_IMR_MASK_RX;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
write_imr(imask, info->regs);
|
2015-11-22 10:28:21 +08:00
|
|
|
|
|
|
|
|
/* Enable the controller */
|
|
|
|
|
set_bit_ssienr(info->regs);
|
|
|
|
|
|
2016-01-27 04:38:44 +08:00
|
|
|
device_sync_call_wait(&spi->sync);
|
2015-12-08 20:30:41 +08:00
|
|
|
|
|
|
|
|
if (spi->error) {
|
|
|
|
|
spi->error = 0;
|
2016-03-10 01:38:02 +08:00
|
|
|
return -EIO;
|
2015-12-08 20:30:41 +08:00
|
|
|
}
|
|
|
|
|
|
2016-03-10 01:01:20 +08:00
|
|
|
return 0;
|
2015-11-22 10:28:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int spi_dw_suspend(struct device *dev)
|
|
|
|
|
{
|
2016-05-08 07:15:28 +08:00
|
|
|
SYS_LOG_DBG("device %p", dev);
|
2015-11-22 10:28:21 +08:00
|
|
|
|
|
|
|
|
_clock_off(dev);
|
|
|
|
|
|
2016-03-10 01:01:20 +08:00
|
|
|
return 0;
|
2015-11-22 10:28:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int spi_dw_resume(struct device *dev)
|
|
|
|
|
{
|
2016-05-08 07:15:28 +08:00
|
|
|
SYS_LOG_DBG("%p", dev);
|
2015-11-22 10:28:21 +08:00
|
|
|
|
|
|
|
|
_clock_on(dev);
|
|
|
|
|
|
2016-03-10 01:01:20 +08:00
|
|
|
return 0;
|
2015-11-22 10:28:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void spi_dw_isr(void *arg)
|
|
|
|
|
{
|
2016-05-16 02:11:16 +08:00
|
|
|
struct device *dev = (struct device *)arg;
|
2015-11-22 10:28:21 +08:00
|
|
|
struct spi_dw_config *info = dev->config->config_info;
|
|
|
|
|
uint32_t error = 0;
|
|
|
|
|
uint32_t int_status;
|
|
|
|
|
|
|
|
|
|
int_status = read_isr(info->regs);
|
|
|
|
|
|
2016-05-08 07:15:28 +08:00
|
|
|
SYS_LOG_DBG("SPI int_status 0x%x - (tx: %d, rx: %d)",
|
2016-02-05 00:02:03 +08:00
|
|
|
int_status, read_txflr(info->regs), read_rxflr(info->regs));
|
2015-11-22 10:28:21 +08:00
|
|
|
|
|
|
|
|
if (int_status & DW_SPI_ISR_ERRORS_MASK) {
|
|
|
|
|
error = 1;
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (int_status & DW_SPI_ISR_RXFIS) {
|
|
|
|
|
pull_data(dev);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (int_status & DW_SPI_ISR_TXEIS) {
|
|
|
|
|
push_data(dev);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
out:
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
clear_interrupts(info->regs);
|
2015-11-22 10:28:21 +08:00
|
|
|
completed(dev, error);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct spi_driver_api dw_spi_api = {
|
|
|
|
|
.configure = spi_dw_configure,
|
|
|
|
|
.slave_select = spi_dw_slave_select,
|
|
|
|
|
.transceive = spi_dw_transceive,
|
|
|
|
|
.suspend = spi_dw_suspend,
|
|
|
|
|
.resume = spi_dw_resume,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
int spi_dw_init(struct device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct spi_dw_config *info = dev->config->config_info;
|
2016-01-21 18:25:26 +08:00
|
|
|
struct spi_dw_data *spi = dev->driver_data;
|
2015-11-22 10:28:21 +08:00
|
|
|
|
|
|
|
|
_clock_config(dev);
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
_clock_on(dev);
|
2015-11-22 10:28:21 +08:00
|
|
|
|
2016-05-16 02:11:16 +08:00
|
|
|
#if 0 /* TODO: Not correct version for every target. Don't check. */
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
#ifndef CONFIG_SOC_QUARK_SE_SS
|
2015-11-22 10:28:21 +08:00
|
|
|
if (read_ssi_comp_version(info->regs) != DW_SSI_COMP_VERSION) {
|
2016-04-15 00:28:34 +08:00
|
|
|
dev->driver_api = NULL;
|
2015-11-22 10:28:21 +08:00
|
|
|
_clock_off(dev);
|
2016-03-10 22:31:02 +08:00
|
|
|
return -EPERM;
|
2015-11-22 10:28:21 +08:00
|
|
|
}
|
2016-05-16 02:11:16 +08:00
|
|
|
#endif
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
#endif
|
2015-11-22 10:28:21 +08:00
|
|
|
|
2016-01-21 18:15:38 +08:00
|
|
|
info->config_func();
|
2015-11-22 10:28:21 +08:00
|
|
|
|
2016-01-27 04:38:44 +08:00
|
|
|
device_sync_call_init(&spi->sync);
|
2015-12-08 20:30:41 +08:00
|
|
|
|
2016-01-19 00:16:24 +08:00
|
|
|
_spi_config_cs(dev);
|
|
|
|
|
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
/* Masking interrupt and making sure controller is disabled */
|
2015-11-22 10:28:21 +08:00
|
|
|
write_imr(DW_SPI_IMR_MASK, info->regs);
|
|
|
|
|
clear_bit_ssienr(info->regs);
|
|
|
|
|
|
2016-05-08 07:15:28 +08:00
|
|
|
SYS_LOG_DBG("Designware SPI driver initialized on device: %p", dev);
|
2015-11-22 10:28:21 +08:00
|
|
|
|
2016-03-10 01:01:20 +08:00
|
|
|
return 0;
|
2015-11-22 10:28:21 +08:00
|
|
|
}
|
|
|
|
|
|
2015-12-11 01:52:56 +08:00
|
|
|
|
2016-05-08 06:57:14 +08:00
|
|
|
#ifdef CONFIG_SPI_0
|
2016-01-21 18:15:38 +08:00
|
|
|
void spi_config_0_irq(void);
|
2015-11-22 10:28:21 +08:00
|
|
|
|
|
|
|
|
struct spi_dw_data spi_dw_data_port_0;
|
|
|
|
|
|
|
|
|
|
struct spi_dw_config spi_dw_config_0 = {
|
2016-05-08 02:48:28 +08:00
|
|
|
.regs = SPI_DW_PORT_0_REGS,
|
2015-11-22 10:28:21 +08:00
|
|
|
#ifdef CONFIG_SPI_DW_CLOCK_GATE
|
2016-05-08 06:57:14 +08:00
|
|
|
.clock_data = UINT_TO_POINTER(CONFIG_SPI_0_CLOCK_GATE_SUBSYS),
|
2015-11-22 10:28:21 +08:00
|
|
|
#endif /* CONFIG_SPI_DW_CLOCK_GATE */
|
2016-01-19 00:16:24 +08:00
|
|
|
#ifdef CONFIG_SPI_DW_CS_GPIO
|
2016-05-08 06:57:14 +08:00
|
|
|
.cs_gpio_name = CONFIG_SPI_0_CS_GPIO_PORT,
|
|
|
|
|
.cs_gpio_pin = CONFIG_SPI_0_CS_GPIO_PIN,
|
2016-01-19 00:16:24 +08:00
|
|
|
#endif
|
2015-11-22 10:28:21 +08:00
|
|
|
.config_func = spi_config_0_irq
|
|
|
|
|
};
|
|
|
|
|
|
2016-05-08 06:57:14 +08:00
|
|
|
DEVICE_AND_API_INIT(spi_dw_port_0, CONFIG_SPI_0_NAME, spi_dw_init,
|
2016-04-15 00:28:34 +08:00
|
|
|
&spi_dw_data_port_0, &spi_dw_config_0,
|
2016-04-17 05:55:43 +08:00
|
|
|
SECONDARY, CONFIG_SPI_INIT_PRIORITY,
|
2016-04-15 00:28:34 +08:00
|
|
|
&dw_spi_api);
|
2015-11-22 10:28:21 +08:00
|
|
|
|
2016-01-21 18:15:38 +08:00
|
|
|
void spi_config_0_irq(void)
|
2016-01-08 16:46:14 +08:00
|
|
|
{
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
#ifdef CONFIG_SPI_DW_INTERRUPT_SINGLE_LINE
|
2016-05-16 02:11:16 +08:00
|
|
|
IRQ_CONNECT(SPI_DW_PORT_0_IRQ, CONFIG_SPI_0_IRQ_PRI,
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS);
|
2016-05-16 02:11:16 +08:00
|
|
|
irq_enable(SPI_DW_PORT_0_IRQ);
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
_spi_int_unmask(SPI_DW_PORT_0_INT_MASK);
|
|
|
|
|
#else /* SPI_DW_INTERRUPT_SEPARATED_LINES */
|
2016-05-08 06:57:14 +08:00
|
|
|
IRQ_CONNECT(IRQ_SPI0_RX_AVAIL, CONFIG_SPI_0_IRQ_PRI,
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS);
|
2016-05-08 06:57:14 +08:00
|
|
|
IRQ_CONNECT(IRQ_SPI0_TX_REQ, CONFIG_SPI_0_IRQ_PRI,
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS);
|
2016-05-08 06:57:14 +08:00
|
|
|
IRQ_CONNECT(IRQ_SPI0_ERR_INT, CONFIG_SPI_0_IRQ_PRI,
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS);
|
|
|
|
|
|
2016-05-08 02:48:28 +08:00
|
|
|
irq_enable(IRQ_SPI0_RX_AVAIL);
|
|
|
|
|
irq_enable(IRQ_SPI0_TX_REQ);
|
|
|
|
|
irq_enable(IRQ_SPI0_ERR_INT);
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
|
|
|
|
|
_spi_int_unmask(SPI_DW_PORT_0_RX_INT_MASK);
|
|
|
|
|
_spi_int_unmask(SPI_DW_PORT_0_TX_INT_MASK);
|
|
|
|
|
_spi_int_unmask(SPI_DW_PORT_0_ERROR_INT_MASK);
|
|
|
|
|
#endif
|
2016-01-08 16:46:14 +08:00
|
|
|
}
|
2016-05-08 06:57:14 +08:00
|
|
|
#endif /* CONFIG_SPI_0 */
|
|
|
|
|
#ifdef CONFIG_SPI_1
|
2016-01-21 18:15:38 +08:00
|
|
|
void spi_config_1_irq(void);
|
2015-11-22 10:28:21 +08:00
|
|
|
|
|
|
|
|
struct spi_dw_data spi_dw_data_port_1;
|
|
|
|
|
|
|
|
|
|
struct spi_dw_config spi_dw_config_1 = {
|
2016-05-08 02:48:28 +08:00
|
|
|
.regs = SPI_DW_PORT_1_REGS,
|
2015-11-22 10:28:21 +08:00
|
|
|
#ifdef CONFIG_SPI_DW_CLOCK_GATE
|
2016-05-08 06:57:14 +08:00
|
|
|
.clock_data = UINT_TO_POINTER(CONFIG_SPI_1_CLOCK_GATE_SUBSYS),
|
2015-11-22 10:28:21 +08:00
|
|
|
#endif /* CONFIG_SPI_DW_CLOCK_GATE */
|
2016-01-19 00:16:24 +08:00
|
|
|
#ifdef CONFIG_SPI_DW_CS_GPIO
|
2016-05-08 06:57:14 +08:00
|
|
|
.cs_gpio_name = CONFIG_SPI_1_CS_GPIO_PORT,
|
|
|
|
|
.cs_gpio_pin = CONFIG_SPI_1_CS_GPIO_PIN,
|
2016-01-19 00:16:24 +08:00
|
|
|
#endif
|
2015-11-22 10:28:21 +08:00
|
|
|
.config_func = spi_config_1_irq
|
|
|
|
|
};
|
|
|
|
|
|
2016-05-08 06:57:14 +08:00
|
|
|
DEVICE_AND_API_INIT(spi_dw_port_1, CONFIG_SPI_1_NAME, spi_dw_init,
|
2016-04-15 00:28:34 +08:00
|
|
|
&spi_dw_data_port_1, &spi_dw_config_1,
|
2016-04-17 05:55:43 +08:00
|
|
|
SECONDARY, CONFIG_SPI_INIT_PRIORITY,
|
2016-04-15 00:28:34 +08:00
|
|
|
&dw_spi_api);
|
2016-01-21 18:15:38 +08:00
|
|
|
|
|
|
|
|
void spi_config_1_irq(void)
|
|
|
|
|
{
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
#ifdef CONFIG_SPI_DW_INTERRUPT_SINGLE_LINE
|
2016-05-16 02:11:16 +08:00
|
|
|
IRQ_CONNECT(SPI_DW_PORT_1_IRQ, CONFIG_SPI_1_IRQ_PRI,
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS);
|
2016-05-16 02:11:16 +08:00
|
|
|
irq_enable(SPI_DW_PORT_1_IRQ);
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
_spi_int_unmask(SPI_DW_PORT_1_INT_MASK);
|
|
|
|
|
#else /* SPI_DW_INTERRUPT_SEPARATED_LINES */
|
2016-05-08 06:57:14 +08:00
|
|
|
IRQ_CONNECT(IRQ_SPI1_RX_AVAIL, CONFIG_SPI_1_IRQ_PRI,
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS);
|
2016-05-08 06:57:14 +08:00
|
|
|
IRQ_CONNECT(IRQ_SPI1_TX_REQ, CONFIG_SPI_1_IRQ_PRI,
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS);
|
2016-05-08 06:57:14 +08:00
|
|
|
IRQ_CONNECT(IRQ_SPI1_ERR_INT, CONFIG_SPI_1_IRQ_PRI,
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS);
|
|
|
|
|
|
2016-05-08 02:48:28 +08:00
|
|
|
irq_enable(IRQ_SPI1_RX_AVAIL);
|
|
|
|
|
irq_enable(IRQ_SPI1_TX_REQ);
|
|
|
|
|
irq_enable(IRQ_SPI1_ERR_INT);
|
spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
|
|
|
|
|
|
|
|
_spi_int_unmask(SPI_DW_PORT_1_RX_INT_MASK);
|
|
|
|
|
_spi_int_unmask(SPI_DW_PORT_1_TX_INT_MASK);
|
|
|
|
|
_spi_int_unmask(SPI_DW_PORT_1_ERROR_INT_MASK);
|
|
|
|
|
#endif
|
2016-01-21 18:15:38 +08:00
|
|
|
}
|
2016-05-08 06:57:14 +08:00
|
|
|
#endif /* CONFIG_SPI_1 */
|