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zephyr/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c

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soc: arm: dts: arm: xilinx: Zynq-7000 SoC init code, device tree data Add SoC-specific code, the basic device tree and Kconfig data as well as the corresponding linker command file for the Xilinx Zynq-7000 family of SoCs. This SoC - either as a QEMU simulation or on actual hardware such as the Avnet/Digilent ZedBoard - is suitable as an ini- tial target for the ARMv7 Cortex-A support. Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2021-07-15 19:05:54 +08:00
/*
* Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
* SPDX-License-Identifier: Apache-2.0
*/
#include <device.h>
#include <devicetree.h>
#include <init.h>
#include <sys/util.h>
#include <arch/arm/aarch32/mmu/arm_mmu.h>
#include "soc.h"
static const struct arm_mmu_region mmu_regions[] = {
MMU_REGION_FLAT_ENTRY("vectors",
0x00000000,
0x1000,
MT_STRONGLY_ORDERED | MPERM_R | MPERM_X),
MMU_REGION_FLAT_ENTRY("slcr",
0xF8000000,
0x1000,
MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
MMU_REGION_FLAT_ENTRY("mpcore",
0xF8F00000,
0x2000,
MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
MMU_REGION_FLAT_ENTRY("ocm",
DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)),
DT_REG_SIZE(DT_CHOSEN(zephyr_ocm)),
MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
/* ARM Arch timer, GIC are covered by the MPCore mapping */
/* UARTs */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart0), okay)
MMU_REGION_FLAT_ENTRY("uart0",
DT_REG_ADDR(DT_NODELABEL(uart0)),
DT_REG_SIZE(DT_NODELABEL(uart0)),
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
MMU_REGION_FLAT_ENTRY("uart1",
DT_REG_ADDR(DT_NODELABEL(uart1)),
DT_REG_SIZE(DT_NODELABEL(uart1)),
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
#endif
/* GEMs */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gem0), okay)
MMU_REGION_FLAT_ENTRY("gem0",
DT_REG_ADDR(DT_NODELABEL(gem0)),
DT_REG_SIZE(DT_NODELABEL(gem0)),
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gem1), okay)
MMU_REGION_FLAT_ENTRY("gem1",
DT_REG_ADDR(DT_NODELABEL(gem1)),
DT_REG_SIZE(DT_NODELABEL(gem1)),
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
#endif
};
const struct arm_mmu_config mmu_config = {
.num_regions = ARRAY_SIZE(mmu_regions),
.mmu_regions = mmu_regions,
};
/**
* @brief Basic hardware initialization of the Zynq-7000 SoC
*
* Performs the basic initialization of the Zynq-7000 SoC.
*
* @return 0
*/
soc: arm: xilinx_zynq7000: Re-organize SoC data and init code Re-organize the SoC family/series/model configuration data so that: * Board definitions can distinguish between the single-core (XC7ZxxxS) and dual-core (XC7Zxxx) ARM Cortex-A9 models. Further descriptions of on-chip resources, in particular relating to the programmable logic capabilities if support of this functionality is to be implemented, can be added at a later time. * Separate SoC initialization code exists for the two series, so that the init code of the XC7Zxxx series can consider SMP while the init code of the single-core XC7ZxxxS series doesn't have to. * Device drivers which don't have to distinguish between the single- and double-core series of the SoC family can use a common configuration item whenever the pre-processor is used to enable Zynq-7000-specific code. Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
2021-11-11 21:29:16 +08:00
static int soc_xlnx_zynq7000s_init(const struct device *arg)
soc: arm: dts: arm: xilinx: Zynq-7000 SoC init code, device tree data Add SoC-specific code, the basic device tree and Kconfig data as well as the corresponding linker command file for the Xilinx Zynq-7000 family of SoCs. This SoC - either as a QEMU simulation or on actual hardware such as the Avnet/Digilent ZedBoard - is suitable as an ini- tial target for the ARMv7 Cortex-A support. Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2021-07-15 19:05:54 +08:00
{
ARG_UNUSED(arg);
NMI_INIT();
return 0;
}
soc: arm: xilinx_zynq7000: Re-organize SoC data and init code Re-organize the SoC family/series/model configuration data so that: * Board definitions can distinguish between the single-core (XC7ZxxxS) and dual-core (XC7Zxxx) ARM Cortex-A9 models. Further descriptions of on-chip resources, in particular relating to the programmable logic capabilities if support of this functionality is to be implemented, can be added at a later time. * Separate SoC initialization code exists for the two series, so that the init code of the XC7Zxxx series can consider SMP while the init code of the single-core XC7ZxxxS series doesn't have to. * Device drivers which don't have to distinguish between the single- and double-core series of the SoC family can use a common configuration item whenever the pre-processor is used to enable Zynq-7000-specific code. Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
2021-11-11 21:29:16 +08:00
SYS_INIT(soc_xlnx_zynq7000s_init, PRE_KERNEL_1,
soc: arm: dts: arm: xilinx: Zynq-7000 SoC init code, device tree data Add SoC-specific code, the basic device tree and Kconfig data as well as the corresponding linker command file for the Xilinx Zynq-7000 family of SoCs. This SoC - either as a QEMU simulation or on actual hardware such as the Avnet/Digilent ZedBoard - is suitable as an ini- tial target for the ARMv7 Cortex-A support. Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2021-07-15 19:05:54 +08:00
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
/* EOF */