66 lines
1.3 KiB
C
66 lines
1.3 KiB
C
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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32U5 processor
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*/
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#include <device.h>
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#include <init.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_icache.h>
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#include <arch/cpu.h>
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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#include <logging/log.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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LOG_MODULE_REGISTER(soc);
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int stm32u5_init(const struct device *arg)
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{
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uint32_t key;
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ARG_UNUSED(arg);
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key = irq_lock();
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/* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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irq_unlock(key);
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/* Enable instruction cache in 1-way (direct mapped cache) */
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LL_ICACHE_SetMode(LL_ICACHE_1WAY);
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LL_ICACHE_Enable();
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 4 MHz from MSIS */
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SystemCoreClock = 4000000;
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/* Enable PWR */
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
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/* Disable USB Type-C dead battery pull-down behavior */
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LL_PWR_DisableUCPDDeadBattery();
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return 0;
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}
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SYS_INIT(stm32u5_init, PRE_KERNEL_1, 0);
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