72 lines
1.6 KiB
YAML
72 lines
1.6 KiB
YAML
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description: Microchip XEC DMA controller
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compatible: "microchip,xec-dmac"
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include: dma-controller.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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pcrs:
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type: array
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required: true
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description: PCR register index and bit position
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girqs:
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type: array
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required: true
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description: Encoded interrupt information
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aggregated-girq:
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type: phandle
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description: |
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If DMA driver uses aggregated interrupt mode
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provide the handle to the GIRQ.
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"#dma-cells":
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const: 2
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"pcr-cells":
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type: int
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const: 2
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"girq-cells":
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type: int
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const: 2
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# #dma-cells : Must be <2>.
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# The 1st cell specifies the DMAC channel to be used for the data transfer.
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# This channel should be unique between all peripherals that are using the
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# DMAC instance.
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# The 2nd cell defines the peripheral trigger which is the source of the transfer.
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# For details on trigger selection and trigger modes, refer to
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# "Transfer Triggers and Actions".
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# See the SoC's reference manual for all the supported request sources.
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#
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# Example of devicetree dma channel configuration:
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#
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# &sercom3 {
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# /* Configure DMA channels for async operation */
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# dmas = <&dmac 10 7>, <&dmac 11 8>;
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# dma-names = "rx", "tx";
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# };
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#
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# In above fragment 10 and 11 represents the different channels used to
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# transfer data between peripheral and ram. The numbers 7/8 are, for instance,
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# uart_rx/tx peripheral trigger for sercom3.
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dma-cells:
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- channel
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- trigsrc
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pcr-cells:
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- regidx
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- bitpos
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girq-cells:
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- girqno
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- girqpos
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