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zephyr/boards/x86/ehl_crb/Kconfig.defconfig

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boards: x86: Add ehl_crb board definition Add initial definition for the Elkhart Lake CRB board. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:10:54 +08:00
# Copyright (c) 2020 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
soc/x86: Clean up EHL kconfigs Cleanup along the same lines as the last change to APL/up_squared. Make sure all hardware configuration is at the board level where it belongs and not in the soc, don't play games with defaulting timer drivers. Unify the configuration where possible and make it clearer which setting goes with which driver. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-05-07 08:57:51 +08:00
if BOARD_EHL_CRB || BOARD_EHL_CRB_SBL
boards: x86: Add ehl_crb board definition Add initial definition for the Elkhart Lake CRB board. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:10:54 +08:00
config BOARD
soc/x86: Clean up EHL kconfigs Cleanup along the same lines as the last change to APL/up_squared. Make sure all hardware configuration is at the board level where it belongs and not in the soc, don't play games with defaulting timer drivers. Unify the configuration where possible and make it clearer which setting goes with which driver. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-05-07 08:57:51 +08:00
default "ehl_crb_sbl" if BOARD_EHL_CRB_SBL
boards: x86: Add ehl_crb board definition Add initial definition for the Elkhart Lake CRB board. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:10:54 +08:00
default "ehl_crb"
config BUILD_OUTPUT_STRIPPED
default y
config MP_NUM_CPUS
default 2
boards: x86: ehl_crb: Add board variant for Slim Bootloader When using Slim Bootloader the UART configuration isn't quite the same as with the UEFI BIOS. In particular, UART2 is hidden in PCIe and is instead accessible using a fixed MMIO address. Interrupts are also not supported for this UART currently. The simplest way to create builds against this special BIOS/bootloader setup seems to be to create a new board variant/definition which lets us provide a custom device tree overlay as well a dedicated Kconfig default configuration. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-23 02:24:35 +08:00
if BOARD_EHL_CRB_SBL
config SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN
depends on SHELL_BACKEND_SERIAL
default n
soc/x86: Clean up EHL kconfigs Cleanup along the same lines as the last change to APL/up_squared. Make sure all hardware configuration is at the board level where it belongs and not in the soc, don't play games with defaulting timer drivers. Unify the configuration where possible and make it clearer which setting goes with which driver. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-05-07 08:57:51 +08:00
endif
config HPET_TIMER
default y
boards: x86: ehl_crb: Add board variant for Slim Bootloader When using Slim Bootloader the UART configuration isn't quite the same as with the UEFI BIOS. In particular, UART2 is hidden in PCIe and is instead accessible using a fixed MMIO address. Interrupts are also not supported for this UART currently. The simplest way to create builds against this special BIOS/bootloader setup seems to be to create a new board variant/definition which lets us provide a custom device tree overlay as well a dedicated Kconfig default configuration. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-23 02:24:35 +08:00
soc/x86: Clean up EHL kconfigs Cleanup along the same lines as the last change to APL/up_squared. Make sure all hardware configuration is at the board level where it belongs and not in the soc, don't play games with defaulting timer drivers. Unify the configuration where possible and make it clearer which setting goes with which driver. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-05-07 08:57:51 +08:00
# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1900000000 if APIC_TSC_DEADLINE_TIMER
default 1900000000 if APIC_TIMER_TSC
default 19200000
if APIC_TIMER
config APIC_TIMER_IRQ
default 24
config APIC_TIMER_TSC_M
default 3
config APIC_TIMER_TSC_N
default 249
endif
endif # BOARD_EHL_CRB || BOARD_EHL_CRB_SBL