63 lines
1.1 KiB
Plaintext
63 lines
1.1 KiB
Plaintext
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/*
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* Copyright (c) 2023 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/intel-ioapic.h>
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#include <mem.h>
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/ {
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chosen {
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu0@0 {
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device_type = "cpu";
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compatible = "intel,ish";
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reg = <0>;
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};
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};
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intc: ioapic@fec00000 {
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compatible = "intel,ioapic";
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reg = <0xfec00000 0x100000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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sram: memory@ff200000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xff200000 DT_SIZE_K(640)>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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hpet: hpet@4700000{
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compatible = "intel,hpet";
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reg = <0x04700000 0x400>;
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interrupt-parent = <&intc>;
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interrupts = <14 IRQ_TYPE_FIXED_LEVEL_HIGH 2>;
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status = "okay";
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};
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uart0: uart@8100000 {
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compatible = "intel,sedi-uart";
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reg = <0x08100000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <23 IRQ_TYPE_LOWEST_EDGE_RISING 6>;
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current-speed = <115200>;
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status = "okay";
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};
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};
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};
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