2021-11-04 21:14:51 +08:00
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# Copyright (c) 2019 Intel Corp.
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# SPDX-License-Identifier: Apache-2.0
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config RISCV_MACHINE_TIMER
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bool "RISCV Machine Timer"
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2022-09-06 23:28:25 +08:00
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default y
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depends on DT_HAS_ANDESTECH_MACHINE_TIMER_ENABLED || \
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DT_HAS_NEORV32_MACHINE_TIMER_ENABLED || \
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DT_HAS_NUCLEI_SYSTIMER_ENABLED || \
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DT_HAS_SIFIVE_CLINT0_ENABLED || \
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DT_HAS_TELINK_MACHINE_TIMER_ENABLED
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2021-11-04 21:14:51 +08:00
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select TICKLESS_CAPABLE
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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This module implements a kernel device driver for the generic RISCV machine
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timer driver. It provides the standard "system clock driver" interfaces.
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2020-03-08 22:21:21 +08:00
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2022-11-01 04:34:19 +08:00
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if RISCV_MACHINE_TIMER
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2020-03-08 22:21:21 +08:00
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config RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER
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int
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default 0
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help
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Specifies the division ratio of the system clock supplied to the Machine Timer.
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A clock obtained by dividing the system clock by a value of [2^N] is
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supplied to the timer. Where N is this parameter's value.
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When N=2, it is divided by 4, and when N=5, it is divided by 32.
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Default case is N=0, this means use system clock as machine timer clock.
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It is normal configuration for RISC-V machine clock.
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This parameter usually depends on the hardware configuration.
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The division ratio should define in devicetree,
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2022-02-24 20:00:55 +08:00
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and it is desirable usage that references it with using a function such as
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2020-03-08 22:21:21 +08:00
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dt_node_int_prop_int from Kconfig. (Tune in the conf file is not preferable.)
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2022-05-10 14:25:44 +08:00
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config RISCV_MACHINE_TIMER_MIN_DELAY
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int
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default 100
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help
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Specifies the minimum number of machine cycles before the RISC-V machine
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time compare register is allowed to be updated by the RISC-V machine timer
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driver.
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2022-11-01 04:34:19 +08:00
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endif
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