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zephyr/boards/riscv/qemu_riscv64/qemu_riscv64.dts

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riscv: add a qemu_riscv64 board This emulates a RISC-V in 64-bit mode on a SiFive FE310 dev board. Memory is tight so a few tests had to be disabled due to the extra memory usage compared to qemu_riscv32. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-07-19 11:07:45 +08:00
/* Copyright (c) 2019 BayLibre SAS */
/* SPDX-License-Identifier: Apache-2.0 */
/dts-v1/;
boards: qemu_riscv64 use virt machine Upgrade board specification to use the VirtIO board. Keeps FPU run-time support disabled since the RISC-V 64-bit FPU support in kernel appears to be non-functional. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2021-01-08 04:16:02 +08:00
#include <virt.dtsi>
riscv: add a qemu_riscv64 board This emulates a RISC-V in 64-bit mode on a SiFive FE310 dev board. Memory is tight so a few tests had to be disabled due to the extra memory usage compared to qemu_riscv32. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-07-19 11:07:45 +08:00
/ {
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
boards: qemu_riscv64 use virt machine Upgrade board specification to use the VirtIO board. Keeps FPU run-time support disabled since the RISC-V 64-bit FPU support in kernel appears to be non-functional. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2021-01-08 04:16:02 +08:00
zephyr,sram = &ram0;
riscv: add a qemu_riscv64 board This emulates a RISC-V in 64-bit mode on a SiFive FE310 dev board. Memory is tight so a few tests had to be disabled due to the extra memory usage compared to qemu_riscv32. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-07-19 11:07:45 +08:00
};
};
&uart0 {
status = "okay";
};