142 lines
3.4 KiB
C
142 lines
3.4 KiB
C
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/*
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* Copyright (c) 2019 SEAL AG
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*
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* Based on NXP K6x soc.c, which is:
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* Copyright (c) 2014-2015 Wind River Systems, Inc.
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <fsl_common.h>
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#include <fsl_clock.h>
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#define PLLFLLSEL_MCGFLLCLK (0)
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#define PLLFLLSEL_MCGPLLCLK (1)
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#define PLLFLLSEL_IRC48MHZ (3)
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#define ER32KSEL_OSC32KCLK (0)
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#define ER32KSEL_LPO1KHZ (3)
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#define PERIPH_CLK_PLLFLLSEL (1)
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#define PERIPH_CLK_OSCERCLK (2)
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#define PERIPH_CLK_MCGIRCLK (3)
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#define RUNM_RUN (0)
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#define RUNM_VLPR (2)
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#define RUNM_HSRUN (3)
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static const osc_config_t osc_config = {
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.freq = CONFIG_OSC_XTAL0_FREQ,
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.capLoad = 0,
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#if defined(CONFIG_OSC_EXTERNAL)
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.workMode = kOSC_ModeExt,
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#elif defined(CONFIG_OSC_LOW_POWER)
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.workMode = kOSC_ModeOscLowPower,
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#elif defined(CONFIG_OSC_HIGH_GAIN)
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.workMode = kOSC_ModeOscHighGain,
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#else
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#error "An oscillator mode must be defined"
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#endif
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.oscerConfig = {
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.enableMode = kOSC_ErClkEnable,
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#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && \
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FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
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.erclkDiv = 0U,
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#endif
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},
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};
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static const mcg_pll_config_t pll0_config = {
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.enableMode = 0U,
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.prdiv = CONFIG_MCG_PRDIV0,
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.vdiv = CONFIG_MCG_VDIV0,
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};
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static const sim_clock_config_t sim_config = {
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/* PLLFLLSEL: select PLL. */
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.pllFllSel = PLLFLLSEL_MCGPLLCLK,
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/* ERCLK32K selection: use system oscillator. */
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.er32kSrc = ER32KSEL_OSC32KCLK,
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.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_K8X_CORE_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV2(CONFIG_K8X_BUS_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV3(CONFIG_K8X_FLEXBUS_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV4(CONFIG_K8X_FLASH_CLOCK_DIVIDER - 1),
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};
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static ALWAYS_INLINE void clk_init(void)
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{
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CLOCK_SetSimSafeDivs();
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CLOCK_InitOsc0(&osc_config);
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CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
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CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0_config);
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CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
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CONFIG_MCG_FCRDIV);
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CLOCK_SetSimConfig(&sim_config);
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/* Divide PLL output frequency by 2 for peripherals */
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CLOCK_SetPllFllSelClock(PLLFLLSEL_MCGPLLCLK, 1, 0);
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#if CONFIG_UART_MCUX_LPUART
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CLOCK_SetLpuartClock(PERIPH_CLK_PLLFLLSEL);
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#endif
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#if CONFIG_USB_KINETIS
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CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, 120000000UL);
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#endif
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}
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static int k8x_init(struct device *arg)
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{
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ARG_UNUSED(arg);
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unsigned int old_level; /* old interrupt lock level */
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#if !defined(CONFIG_ARM_MPU)
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u32_t temp_reg;
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#endif /* !CONFIG_ARM_MPU */
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/* Disable interrupts */
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old_level = irq_lock();
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/* release I/O power hold to allow normal run state */
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PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
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#if !defined(CONFIG_ARM_MPU)
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/*
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* Disable memory protection and clear slave port errors.
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* Note that the K8x does not implement the optional ARMv7-M memory
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* protection unit (MPU), specified by the architecture (PMSAv7), in the
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* Cortex-M4 core. Instead, the processor includes its own MPU module.
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*/
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temp_reg = SYSMPU->CESR;
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temp_reg &= ~SYSMPU_CESR_VLD_MASK;
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temp_reg |= SYSMPU_CESR_SPERR_MASK;
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SYSMPU->CESR = temp_reg;
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#endif /* !CONFIG_ARM_MPU */
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/* Initialize system clocks and PLL */
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clk_init();
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/*
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* Install default handler that simply resets the CPU if
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* configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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/* Restore interrupt state */
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irq_unlock(old_level);
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return 0;
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}
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SYS_INIT(k8x_init, PRE_KERNEL_1, 0);
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