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zephyr/boards/x86/acrn/acrn_ehl_crb_defconfig

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boards: x86: acrn : Add configurations for acrn_ehl_crb Adding acrn configurations specific to the platform on which acrn boots zephyr, Only the EHL specifc configurations for now. Keeping the HW clock frequency to 1900Mhz for EHL and using the new APIc timer driver. Signed-off-by: Aastha Grover <aastha.grover@intel.com>
2020-12-17 09:06:31 +08:00
# SPDX-License-Identifier: Apache-2.0
CONFIG_SOC_IA32=y
CONFIG_BOARD_ACRN=y
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_X2APIC=y
boards: acrn_ehl_crb: Add PCIe to defconfig A lot of basic functionality depends on PCIe, so enable it in the defconfig. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-07-12 23:42:07 +08:00
CONFIG_PCIE=y
boards: x86: acrn : Add configurations for acrn_ehl_crb Adding acrn configurations specific to the platform on which acrn boots zephyr, Only the EHL specifc configurations for now. Keeping the HW clock frequency to 1900Mhz for EHL and using the new APIc timer driver. Signed-off-by: Aastha Grover <aastha.grover@intel.com>
2020-12-17 09:06:31 +08:00
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_NS16550=y
CONFIG_UART_CONSOLE=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1900000000
CONFIG_BUILD_OUTPUT_BIN=y
CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n
boards: x86: increase VM size on PC-like These are all PC systems which have large amounts of memory which needs to be mapped at runtime (most are 2GB). Increase the address space size accordingly, adding an extra 8MB for mappings. The ACRN target has 8MB, give it 16MB of VM. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-24 06:12:27 +08:00
CONFIG_KERNEL_VM_SIZE=0x1000000
boards: x86: oneApi and LLVM objcopy do not support --gap-fill Work around the fact that llvm objcopy does not support --gap-fill right now. This should be done on the toolchain level at some point, it is currently not possible however. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-03-20 05:44:05 +08:00
CONFIG_BUILD_NO_GAP_FILL=y
boards: acrn_ehl_crb: Use the new APIC_TSC_DEADLINE timer driver Update to use this driver as this CPU has the needed APIC support. Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
2021-05-06 09:11:57 +08:00
CONFIG_APIC_TSC_DEADLINE_TIMER=y
acrn_ehl_crb: fix the incorrect configuration of timer IRQ priority The default CONFIG_APIC_TIMER_IRQ_PRIORITY is 4, but it should be 1 for ACRN. That's why the testcase failed due to no timer interrupt was triggered. And we also temporary adjust the testing IRQ for dynamic isr due to it conflict with the IRQ of the APIC TSC deadline TIMER. Fixes #36203. Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
2021-08-02 23:14:39 +08:00
CONFIG_APIC_TIMER_IRQ_PRIORITY=1
boards/x86/acrn_ehl_crb: Enable SMP by default SMP is working now, make a 2-cpu configuration default for this device. Note that this requires changes to the default ACRN build configuration! In hybrid.xml, you need to specify multiple physical CPUs for the VM to uses, e.g.: <vm id="0"> ... <cpu_affinity> <pcpu_id>0</pcpu_id> <pcpu_id>1</pcpu_id> </cpu_affinity> </vm> Failing to build with this change will result in the system hanging at boot trying to start up a CPU that won't run. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-05-28 20:11:20 +08:00
CONFIG_SMP=y