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zephyr/soc/riscv/riscv-privilege/miv/soc.h

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license: cleanup: add SPDX Apache-2.0 license identifier Update the files which contain no license information with the 'Apache-2.0' SPDX license identifier. Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of Zephyr, which is Apache version 2. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-06 21:08:09 +08:00
/*
* SPDX-License-Identifier: Apache-2.0
*/
riscv32: riscv-privilege: Microsemi Mi-V support This commit adds support for Microsemi Mi-V RISC-V softcore CPU running on the M2GL025 IGLOO2 FPGA development board. signed-off-by: Karol Gugala <kgugala@antmicro.com>
2018-06-11 01:02:14 +08:00
#ifndef __RISCV32_MIV_SOC_H_
#define __RISCV32_MIV_SOC_H_
#include <soc_common.h>
dts: Rename generated_dts_board*.{h,conf} to devicetree*.{h,conf} generated_dts_board.h is pretty redundant and confusing as a name. Call it devicetree.h instead. dts.h would be another option, but DTS stands for "devicetree source" and is the source code format, so it's a bit confusing too. The replacement was done by grepping for 'generated_dts_board' and 'GENERATED_DTS_BOARD'. Two build diagram and input-output SVG files were updated as well, along with misc. documentation. hal_ti, mcuboot, and ci-tools updates are included too, in the west.yml update. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-01-16 20:29:53 +08:00
#include <devicetree.h>
riscv32: riscv-privilege: Microsemi Mi-V support This commit adds support for Microsemi Mi-V RISC-V softcore CPU running on the M2GL025 IGLOO2 FPGA development board. signed-off-by: Karol Gugala <kgugala@antmicro.com>
2018-06-11 01:02:14 +08:00
/* GPIO Interrupts */
interrupt: Convert RISC-V plic to use multi-level irq support Utilize the multi-level irq infrastructure and replace custom handling for PLIC on riscv-privilege SoCs. The old code offset IRQs in drivers and various places with RISCV_MAX_GENERIC_IRQ. Instead utilize Zephyr's encoded IRQ and replace offsets in drivers with the IRQ define from DTS. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 12:01:37 +08:00
#define MIV_GPIO_0_IRQ (0)
#define MIV_GPIO_1_IRQ (1)
#define MIV_GPIO_2_IRQ (2)
#define MIV_GPIO_3_IRQ (3)
#define MIV_GPIO_4_IRQ (4)
#define MIV_GPIO_5_IRQ (5)
#define MIV_GPIO_6_IRQ (6)
#define MIV_GPIO_7_IRQ (7)
#define MIV_GPIO_8_IRQ (8)
#define MIV_GPIO_9_IRQ (9)
#define MIV_GPIO_10_IRQ (10)
#define MIV_GPIO_11_IRQ (11)
#define MIV_GPIO_12_IRQ (12)
#define MIV_GPIO_13_IRQ (13)
#define MIV_GPIO_14_IRQ (14)
#define MIV_GPIO_15_IRQ (15)
#define MIV_GPIO_16_IRQ (16)
#define MIV_GPIO_17_IRQ (17)
#define MIV_GPIO_18_IRQ (18)
#define MIV_GPIO_19_IRQ (19)
#define MIV_GPIO_20_IRQ (20)
#define MIV_GPIO_21_IRQ (21)
#define MIV_GPIO_22_IRQ (22)
#define MIV_GPIO_23_IRQ (23)
#define MIV_GPIO_24_IRQ (24)
#define MIV_GPIO_25_IRQ (25)
#define MIV_GPIO_26_IRQ (26)
#define MIV_GPIO_27_IRQ (27)
#define MIV_GPIO_28_IRQ (28)
#define MIV_GPIO_29_IRQ (29)
#define MIV_GPIO_30_IRQ (30)
#define MIV_GPIO_31_IRQ (31)
riscv32: riscv-privilege: Microsemi Mi-V support This commit adds support for Microsemi Mi-V RISC-V softcore CPU running on the M2GL025 IGLOO2 FPGA development board. signed-off-by: Karol Gugala <kgugala@antmicro.com>
2018-06-11 01:02:14 +08:00
/* UART Configuration */
#define MIV_UART_0_LINECFG 0x1
/* GPIO Configuration */
#define MIV_GPIO_0_BASE_ADDR 0x70002000
/* Clock controller. */
#define PRCI_BASE_ADDR 0x44000000
/* Timer configuration */
#define RISCV_MTIME_BASE 0x4400bff8
#define RISCV_MTIMECMP_BASE 0x44004000
/* lib-c hooks required RAM defined variables */
devicetree: Remove DT_SRAM_{BASE_ADDRESS,SIZE}, use CONFIG_* versions The SRAM address and size are currently available as both DT_SRAM_{BASE_ADDRESS,SIZE} and as CONFIG_SRAM_{BASE_ADDRESS,SIZE} (via the Kconfig preprocessor). Use the CONFIG_SRAM_* versions everywhere, and remove generation of the DT_SRAM_* versions from gen_defines.py. The Kconfig symbols currently depend on 'ARC || ARM || NIOS2 || X86'. Not sure why, so I removed it. It looks like no configuration files set CONFIG_SRAM_* at the moment, so another option might be to use the DT_* symbols everywhere instead. Some Kconfig.defconfig.series files add defaults to them though. Also improve the help texts for CONFIG_SRAM_* to say that they normally come from devicetree rather than configuration files. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-12-26 23:08:19 +08:00
#define RISCV_RAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define RISCV_RAM_SIZE KB(CONFIG_SRAM_SIZE)
riscv32: riscv-privilege: Microsemi Mi-V support This commit adds support for Microsemi Mi-V RISC-V softcore CPU running on the M2GL025 IGLOO2 FPGA development board. signed-off-by: Karol Gugala <kgugala@antmicro.com>
2018-06-11 01:02:14 +08:00
#endif /* __RISCV32_MIV_SOC_H_ */