92 lines
3.3 KiB
C
92 lines
3.3 KiB
C
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/* intel_spi_priv.h - Intel's SPI driver private definitions */
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __INTEL_SPI_PRIV_H__
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#define __INTEL_SPI_PRIV_H__
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/* Registers */
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#define INTEL_SPI_REG_SSCR0 (0x00)
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#define INTEL_SPI_REG_SSRC1 (0x04)
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#define INTEL_SPI_REG_SSSR (0x08)
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#define INTEL_SPI_REG_SSDR (0x10)
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#define INTEL_SPI_REG_DDS_RATE (0x28)
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#define INTEL_SPI_CLK_DIV_MASK (0x000000ff)
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#define INTEL_SPI_DDS_RATE_MASK (0xffffff00)
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/* SSCR0 settings */
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#define INTEL_SPI_SSCR0_DSS(__bpw) ((__bpw) - 1)
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#define INTEL_SPI_SSCR0_SSE (0x1 << 7)
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#define INTEL_SPI_SSCR0_SSE_BIT (7)
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#define INTEL_SPI_SSCR0_SCR(__msf) \
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((__msf && INTEL_SPI_CLK_DIV_MASK) << 8)
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/* SSCR1 settings */
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#define INTEL_SPI_SSCR1_RIE (0x1)
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#define INTEL_SPI_SSCR1_TIE (0x1 << 1)
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#define INTEL_SPI_SSCR1_LBM (0x1 << 2)
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#define INTEL_SPI_SSCR1_SPO (0x1 << 3)
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#define INTEL_SPI_SSCR1_SPH (0x1 << 4)
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#define INTEL_SPI_SSCR1_TFT(__tft) \
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(((__tft) - 1) << 6)
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#define INTEL_SPI_SSCR1_RFT(__rft) \
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(((__rft) - 1) << 11)
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#define INTEL_SPI_SSCR1_EFWR (0x1 << 16)
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#define INTEL_SPI_SSCR1_STRF (0x1 << 17)
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#define INTEL_SPI_SSCR1_TFT_DFLT (8)
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#define INTEL_SPI_SSCR1_RFT_DFLT (8)
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/* SSSR settings */
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#define INTEL_SPI_SSSR_TNF (0x4)
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#define INTEL_SPI_SSSR_RNE (0x8)
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#define INTEL_SPI_SSSR_TFS (0x20)
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#define INTEL_SPI_SSSR_RFS (0x40)
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#define INTEL_SPI_SSSR_ROR (0x80)
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#define INTEL_SPI_SSSR_TFL_MASK (0x1f << 8)
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#define INTEL_SPI_SSSR_TFL_EMPTY (0x00)
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#define INTEL_SPI_SSSR_RFL_MASK (0x1f << 13)
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#define INTEL_SPI_SSSR_RFL_EMPTY (0x1f)
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#define INTEL_SPI_SSSR_TFL(__status) \
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((__status & INTEL_SPI_SSSR_TFL_MASK) >> 8)
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#define INTEL_SPI_SSSR_RFL(__status) \
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((__status & INTEL_SPI_SSSR_RFL_MASK) >> 13)
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#define INTEL_SPI_SSSR_BSY_BIT (4)
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/* DSS_RATE settings */
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#define INTEL_SPI_DSS_RATE(__msf) \
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((__msf && (INTEL_SPI_DDS_RATE_MASK)) >> 8)
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#endif /* __INTEL_SPI_PRIV_H__ */
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