2015-11-22 20:23:41 +08:00
|
|
|
/*
|
|
|
|
* Copyright (c) 2015 Intel Corporation
|
|
|
|
*
|
|
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
|
|
* you may not use this file except in compliance with the License.
|
|
|
|
* You may obtain a copy of the License at
|
|
|
|
*
|
|
|
|
* http://www.apache.org/licenses/LICENSE-2.0
|
|
|
|
*
|
|
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
|
|
* See the License for the specific language governing permissions and
|
|
|
|
* limitations under the License.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <device.h>
|
|
|
|
#include <init.h>
|
2015-12-17 21:54:35 +08:00
|
|
|
#include "soc.h"
|
2015-11-22 20:23:41 +08:00
|
|
|
|
2015-11-13 06:00:47 +08:00
|
|
|
#if CONFIG_IPM_QUARK_SE
|
|
|
|
#include <ipm.h>
|
|
|
|
#include <ipm/ipm_quark_se.h>
|
2015-11-22 20:23:41 +08:00
|
|
|
|
2015-11-13 06:00:47 +08:00
|
|
|
static int arc_quark_se_ipm_init(void)
|
2015-11-22 20:23:41 +08:00
|
|
|
{
|
2016-08-17 01:58:40 +08:00
|
|
|
IRQ_CONNECT(QUARK_SE_IPM_INTERRUPT, CONFIG_QUARK_SE_SS_IPM_IRQ_PRI,
|
2016-01-08 16:46:14 +08:00
|
|
|
quark_se_ipm_isr, NULL, 0);
|
2015-11-13 06:00:47 +08:00
|
|
|
irq_enable(QUARK_SE_IPM_INTERRUPT);
|
2016-03-22 04:33:24 +08:00
|
|
|
return 0;
|
2015-11-22 20:23:41 +08:00
|
|
|
}
|
|
|
|
|
2015-11-13 06:00:47 +08:00
|
|
|
static struct quark_se_ipm_controller_config_info ipm_controller_config = {
|
|
|
|
.controller_init = arc_quark_se_ipm_init
|
2015-11-22 20:23:41 +08:00
|
|
|
};
|
2016-04-15 00:28:35 +08:00
|
|
|
DEVICE_AND_API_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize,
|
2016-01-29 03:48:47 +08:00
|
|
|
NULL, &ipm_controller_config,
|
2016-04-15 00:28:35 +08:00
|
|
|
SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
|
|
|
&ipm_quark_se_api_funcs);
|
2015-11-22 20:23:41 +08:00
|
|
|
|
2015-11-13 06:00:47 +08:00
|
|
|
#if CONFIG_IPM_CONSOLE_SENDER
|
|
|
|
#include <console/ipm_console.h>
|
|
|
|
QUARK_SE_IPM_DEFINE(quark_se_ipm4, 4, QUARK_SE_IPM_OUTBOUND);
|
2015-11-22 20:23:41 +08:00
|
|
|
|
2015-11-13 06:00:47 +08:00
|
|
|
struct ipm_console_sender_config_info quark_se_ipm_sender_config = {
|
|
|
|
.bind_to = "quark_se_ipm4",
|
|
|
|
.flags = IPM_CONSOLE_PRINTK | IPM_CONSOLE_STDOUT,
|
2015-11-22 20:23:41 +08:00
|
|
|
};
|
2016-01-29 03:48:47 +08:00
|
|
|
DEVICE_INIT(ipm_console, "ipm_console", ipm_console_sender_init,
|
|
|
|
NULL, &quark_se_ipm_sender_config,
|
2016-03-29 05:05:33 +08:00
|
|
|
SECONDARY, CONFIG_IPM_CONSOLE_INIT_PRIORITY);
|
2015-11-22 20:23:41 +08:00
|
|
|
|
2015-11-13 06:00:47 +08:00
|
|
|
#endif /* CONFIG_IPM_CONSOLE_SENDER */
|
|
|
|
#endif /* CONFIG_IPM_QUARK_SE */
|
2015-12-18 06:08:33 +08:00
|
|
|
|
2015-12-19 03:04:54 +08:00
|
|
|
#ifdef CONFIG_UART_NS16550
|
|
|
|
|
|
|
|
static int uart_ns16550_init(struct device *dev)
|
|
|
|
{
|
|
|
|
ARG_UNUSED(dev);
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_NS16550_PORT_0
|
2016-03-30 02:01:11 +08:00
|
|
|
sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_0_INT_MASK),
|
2015-12-19 03:04:54 +08:00
|
|
|
INT_ENABLE_ARC_BIT_POS);
|
|
|
|
#endif /* CONFIG_UART_NS16550_PORT_0 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_NS16550_PORT_1
|
2016-03-30 02:01:11 +08:00
|
|
|
sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_1_INT_MASK),
|
2015-12-19 03:04:54 +08:00
|
|
|
INT_ENABLE_ARC_BIT_POS);
|
|
|
|
#endif /* CONFIG_UART_NS16550_PORT_1 */
|
|
|
|
|
2016-03-22 04:33:24 +08:00
|
|
|
return 0;
|
2015-12-19 03:04:54 +08:00
|
|
|
}
|
|
|
|
|
2016-01-29 04:16:31 +08:00
|
|
|
SYS_INIT(uart_ns16550_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
|
2015-12-19 03:04:54 +08:00
|
|
|
|
|
|
|
#endif /* CONFIG_UART_NS16550 */
|