2015-06-15 21:20:24 +08:00
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# Kconfig - interrupt controller configuration options
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#
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# Copyright (c) 2015 Intel Corporation
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#
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2015-10-07 00:00:37 +08:00
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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2015-06-15 21:20:24 +08:00
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#
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2015-10-07 00:00:37 +08:00
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# http://www.apache.org/licenses/LICENSE-2.0
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2015-06-15 21:20:24 +08:00
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#
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2015-10-07 00:00:37 +08:00
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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2015-06-15 21:20:24 +08:00
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#
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menu "Interrupt Controllers"
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2015-06-06 00:11:24 +08:00
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config LOAPIC
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bool "LOAPIC"
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default n
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2015-07-29 01:24:23 +08:00
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select IOAPIC
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2015-10-09 18:20:52 +08:00
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depends on X86
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2015-06-06 00:11:24 +08:00
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help
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This option selects local APIC as the interrupt controller.
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2015-07-28 01:56:53 +08:00
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config LOAPIC_BASE_ADDRESS
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hex "Local APIC Base Address"
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default 0xFEE00000
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2015-07-31 18:57:00 +08:00
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depends on LOAPIC || MVIC
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2015-07-28 01:56:53 +08:00
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help
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This option specifies the base address of the Local APIC device.
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2015-12-10 06:53:41 +08:00
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config LOAPIC_SPURIOUS_VECTOR
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bool "Handle LOAPIC spurious interrupts"
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default n
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depends on LOAPIC
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help
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A special situation may occur when a processor raises its task
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priority to be greater than or equal to the level of the
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interrupt for which the processor INTR signal is currently being
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asserted. If at the time the INTA cycle is issued, the
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interrupt that was to be dispensed has become masked (programmed
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by software), the local APIC will deliver a spurious-interrupt
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vector. Dispensing the spurious-interrupt vector does not affect
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the ISR, so the handler for this vector should return without an EOI.
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From x86 manual Volume 3 Section 10.9.
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config LOAPIC_SPURIOUS_VECTOR_ID
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int "LOAPIC spurious vector ID"
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default -1
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depends on LOAPIC_SPURIOUS_VECTOR
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help
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IDT vector to use for spurious LOAPIC interrupts. Note that some
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arches (P6, Pentium) ignore the low 4 bits and fix them at 0xF.
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If this value is left at -1 the last entry in the IDT will be used.
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2015-07-23 23:46:25 +08:00
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config IOAPIC
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2015-08-11 21:08:59 +08:00
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bool "IO-APIC"
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default y
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depends on LOAPIC
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2015-06-06 01:48:18 +08:00
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help
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This option signifies that the target has an IO-APIC device. This
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capability allows IO-APIC-dependent code to be included.
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2015-08-11 21:08:59 +08:00
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config IOAPIC_DEBUG
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bool "IO-APIC Debugging"
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default n
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depends on IOAPIC
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help
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Enable debugging for IO-APIC driver.
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2015-07-28 01:56:53 +08:00
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config IOAPIC_BASE_ADDRESS
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hex "IO-APIC Base Address"
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default 0xFEC00000
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2015-07-31 18:57:00 +08:00
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depends on IOAPIC || MVIC
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2015-07-28 01:56:53 +08:00
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help
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This option specifies the base address of the IO-APIC device.
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config IOAPIC_NUM_RTES
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int "Number of Redirection Table Entries available"
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default 24
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depends on IOAPIC
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help
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This option indicates the maximum number of Redirection Table Entries
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(RTEs) (one per IRQ available to the IO-APIC) made available to the
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kernel, regardless of the number provided by the hardware itself. For
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most efficient usage of memory, it should match the number of IRQ lines
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needed by devices connected to the IO-APIC.
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2015-07-31 18:57:00 +08:00
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config MVIC
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bool "Intel Quark D2000 Interrupt Controller (MVIC)"
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default n
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2015-10-09 18:20:52 +08:00
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depends on X86
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2015-07-31 18:57:00 +08:00
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help
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The MVIC (Intel Quark microcontroller D2000 Interrupt Controller) is
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configured by default to support 32 external interrupt lines. Unlike the
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traditional IA LAPIC/IOAPIC, the interrupt vectors in MVIC are fixed and
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not programmable. In addition, the priorities of these interrupt
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lines are also fixed.
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2015-06-20 21:26:06 +08:00
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config ARCV2_INTERRUPT_UNIT
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bool "ARCv2 Interrupt Unit"
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default y
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depends on ARC
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help
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The ARCv2 interrupt unit has 16 allocated exceptions associated with
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vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255.
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The interrupt unit is optional in the ARCv2-based processors. When
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building a processor, you can configure the processor to include an
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interrupt unit. The ARCv2 interrupt unit is highly programmable.
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2015-06-15 21:20:24 +08:00
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endmenu
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