zephyr/soc/arm64/nxp_layerscape/ls1046a/Kconfig.soc

#
# Copyright 2021 NXP
#
# SPDX-License-Identifier: Apache-2.0
#

choice
prompt "NXP Layerscpae LS1046A SoC"
depends on SOC_SERIES_LS1046A

config SOC_LS1046A
	bool "NXP ls1046a"
	select ARM64
	select CPU_CORTEX_A72
	select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS

endchoice
soc: arm64: add NXP ls1046a support NXP ls1046a is SoC includes the following functions and features: 1. Four 32/64-bit Arm v8 A72 CPUs 2. Cache coherent interconnect (CCI-400) 3. One 32/64-bit DDR4 SDRAM memory controller with ECC 4. Peripheral interfaces include DPAA network, PCIe, USB, SPI, GPIO, UART, SDHC, IFC, LPUART ... Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> 2021-04-02 11:12:03 +08:00			`#`
			`# Copyright 2021 NXP`
			`#`
			`# SPDX-License-Identifier: Apache-2.0`
			`#`

			`choice`
			`prompt "NXP Layerscpae LS1046A SoC"`
			`depends on SOC_SERIES_LS1046A`

			`config SOC_LS1046A`
			`bool "NXP ls1046a"`
			`select ARM64`
			`select CPU_CORTEX_A72`
timer: allow for configuring it out Some configurations have the system timer driver hardwired in. Let's make them compatible with CONFIG_SYS_CLOCK_EXISTS=n. Signed-off-by: Nicolas Pitre <npitre@baylibre.com> 2023-08-03 10:20:05 +08:00			`select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS`
soc: arm64: add NXP ls1046a support NXP ls1046a is SoC includes the following functions and features: 1. Four 32/64-bit Arm v8 A72 CPUs 2. Cache coherent interconnect (CCI-400) 3. One 32/64-bit DDR4 SDRAM memory controller with ECC 4. Peripheral interfaces include DPAA network, PCIe, USB, SPI, GPIO, UART, SDHC, IFC, LPUART ... Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> 2021-04-02 11:12:03 +08:00
			`endchoice`