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zephyr/dts/arm/nxp/nxp_rt1060.dtsi

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dts: arm: nxp: rt: Create dedicated rt1060 dtsi i.MX-RT1060 has 512KB additional on-chip RAM mapped at 0x20280000. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-12 16:32:32 +08:00
/*
* Copyright (c) 2019, Linaro
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <nxp/nxp_rt.dtsi>
dts: arm: nxp: rt106x: Unified OCRAM node The iMX RT1060 and RT1064 have additional dedicated 512KB on-chip ram. This OCRAM2 is mapped at 0x20200000, formerly OCRAM1 (flexram) mapping which is moved to 0x20280000 in order to guarentee global OCRAM memory continuity regardless OCRAM1 size configuration (256KB by default). In default configuration, this gives 768KB (512+256) on-chip ram: 0x20200000 to 0x202BFFFF. OCRAM2: 0x20200000 - 0x2027FFFF OCRAM1(FlexRam): 0x2028FFFF - 0x202BFFFF Add this memory region as a single node in the rt1060 device tree. Note: MPU expects power of two memory region, in case of 768KB, let the MPU configure 1MB instead. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-15 17:08:15 +08:00
/* i.MX rt1060 has two continuous on-chip RAM, one is part of the
* FlexRAM mapped at 0x20280000 (vs 0x20280000 on rt1050) and is
* configurable (256KB by defaults), the other one is dedicated 512KB
* ram (OCRAM2) mapped at 0x20200000. In order to have a continuous
* region, we describe them in one 768Kb unique node.
*/
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 23:03:32 +08:00
&ocram {
dts: arm: nxp: rt106x: Unified OCRAM node The iMX RT1060 and RT1064 have additional dedicated 512KB on-chip ram. This OCRAM2 is mapped at 0x20200000, formerly OCRAM1 (flexram) mapping which is moved to 0x20280000 in order to guarentee global OCRAM memory continuity regardless OCRAM1 size configuration (256KB by default). In default configuration, this gives 768KB (512+256) on-chip ram: 0x20200000 to 0x202BFFFF. OCRAM2: 0x20200000 - 0x2027FFFF OCRAM1(FlexRam): 0x2028FFFF - 0x202BFFFF Add this memory region as a single node in the rt1060 device tree. Note: MPU expects power of two memory region, in case of 768KB, let the MPU configure 1MB instead. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-15 17:08:15 +08:00
compatible = "mmio-sram";
dts: arm: Use DT_SIZE macros for nxp internal memories Refactors nxp i.mx, kinetis, and lpc soc-level device trees to use DT_SIZE_K and DT_SIZE_M macros to define internal memory sizes. This is self documenting and easier to read. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-10-22 02:41:50 +08:00
reg = <0x20200000 DT_SIZE_K(768)>;
dts: arm: nxp: rt: Create dedicated rt1060 dtsi i.MX-RT1060 has 512KB additional on-chip RAM mapped at 0x20280000. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-12 16:32:32 +08:00
};
drivers: eth: eth_mcux: Add 2nd Ethernet controller to RT1060 device tree Add eth1 in dtsi and defines for the second controller in fixup. Signed-off-by: Armand Ciejak <armandciejak@users.noreply.github.com>
2020-03-05 21:23:48 +08:00
/* i.MX rt1060 has a second Ethernet controller. */
/ {
soc {
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 23:03:32 +08:00
enet2: ethernet@402d4000 {
drivers: eth: eth_mcux: Add 2nd Ethernet controller to RT1060 device tree Add eth1 in dtsi and defines for the second controller in fixup. Signed-off-by: Armand Ciejak <armandciejak@users.noreply.github.com>
2020-03-05 21:23:48 +08:00
compatible = "nxp,kinetis-ethernet";
reg = <0x402D4000 0x628>;
interrupts = <152 0>;
interrupt-names = "COMMON";
status = "disabled";
label = "ETH_1";
ptp {
compatible = "nxp,kinetis-ptp";
status = "disabled";
interrupts = <153 0>;
interrupt-names = "IEEE1588_TMR";
};
};
};
};