OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/include/drivers/clock_control/stm32f1_clock_control.h

57 lines
2.0 KiB
C
Raw Normal View History

clock_control/stm32f10x: introduce driver for STM32F10x RCC The patch adds a driver for STM32F10x series RCC (Reset and Clock Control) subsystem. The module is primarily responsible for setting up of MCU's clock tree. In particular the driver sets up SYSCLK, PLL (with source configuration), AHB prescaler, and APB1/APB2 prescalers. As part of this functionality, the subsystem can enable/disable clock signal for particular peripherals, thus reducing the power consumption of the MCU. The driver implements clock control driver API. However, subsystem IDs being HW specific are exposed in driver public header that must be included by callers. The driver registers a single device using a common name STM32_CLOCK_CONTROL_NAME. The device is initialized at the PRIMARY level with priority 1. This allows the initialization to take place right after SoC initialization routine. The driver depends on selection of SOC_STM32F1X config option and is MCU specific. Change-Id: I8bea5db20726a24bce7b7ffe0b95de543240429a Origin: Original Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-03 22:33:04 +08:00
/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
*
license: Replace Apache boilerplate with SPDX tag Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 09:01:01 +08:00
* SPDX-License-Identifier: Apache-2.0
clock_control/stm32f10x: introduce driver for STM32F10x RCC The patch adds a driver for STM32F10x series RCC (Reset and Clock Control) subsystem. The module is primarily responsible for setting up of MCU's clock tree. In particular the driver sets up SYSCLK, PLL (with source configuration), AHB prescaler, and APB1/APB2 prescalers. As part of this functionality, the subsystem can enable/disable clock signal for particular peripherals, thus reducing the power consumption of the MCU. The driver implements clock control driver API. However, subsystem IDs being HW specific are exposed in driver public header that must be included by callers. The driver registers a single device using a common name STM32_CLOCK_CONTROL_NAME. The device is initialized at the PRIMARY level with priority 1. This allows the initialization to take place right after SoC initialization routine. The driver depends on selection of SOC_STM32F1X config option and is MCU specific. Change-Id: I8bea5db20726a24bce7b7ffe0b95de543240429a Origin: Original Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-03 22:33:04 +08:00
*/
#ifndef _STM32F1_CLOCK_CONTROL_H_
#define _STM32F1_CLOCK_CONTROL_H_
/**
doc: clock_control/stm32f1: Fix @file tag The @file tag should follow by a file (or nothing for current file), instead of file description. Fix it by separating the description. Change-Id: Iabe3550568cdfdda6ad71be6fab3e8b5dfbeb940 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-04-16 04:11:42 +08:00
* @file
*
* @brief Clock subsystem IDs for STM32F1 family
clock_control/stm32f10x: introduce driver for STM32F10x RCC The patch adds a driver for STM32F10x series RCC (Reset and Clock Control) subsystem. The module is primarily responsible for setting up of MCU's clock tree. In particular the driver sets up SYSCLK, PLL (with source configuration), AHB prescaler, and APB1/APB2 prescalers. As part of this functionality, the subsystem can enable/disable clock signal for particular peripherals, thus reducing the power consumption of the MCU. The driver implements clock control driver API. However, subsystem IDs being HW specific are exposed in driver public header that must be included by callers. The driver registers a single device using a common name STM32_CLOCK_CONTROL_NAME. The device is initialized at the PRIMARY level with priority 1. This allows the initialization to take place right after SoC initialization routine. The driver depends on selection of SOC_STM32F1X config option and is MCU specific. Change-Id: I8bea5db20726a24bce7b7ffe0b95de543240429a Origin: Original Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-03 22:33:04 +08:00
*/
enum {
/* APB1 */
STM32F10X_CLOCK_SUBSYS_TIM2 = 1 << 0,
STM32F10X_CLOCK_SUBSYS_TIM3 = 1 << 1,
STM32F10X_CLOCK_SUBSYS_TIM4 = 1 << 2,
STM32F10X_CLOCK_SUBSYS_TIM5 = 1 << 3,
STM32F10X_CLOCK_SUBSYS_TIM6 = 1 << 4,
STM32F10X_CLOCK_SUBSYS_TIM7 = 1 << 5,
STM32F10X_CLOCK_SUBSYS_WWDG = 1 << 11,
STM32F10X_CLOCK_SUBSYS_SPI2 = 1 << 14,
STM32F10X_CLOCK_SUBSYS_SPI3 = 1 << 15,
STM32F10X_CLOCK_SUBSYS_USART2 = 1 << 17,
STM32F10X_CLOCK_SUBSYS_USART3 = 1 << 18,
STM32F10X_CLOCK_SUBSYS_UART4 = 1 << 19,
STM32F10X_CLOCK_SUBSYS_UART5 = 1 << 20,
STM32F10X_CLOCK_SUBSYS_I2C1 = 1 << 21,
STM32F10X_CLOCK_SUBSYS_I2C2 = 1 << 22,
STM32F10X_CLOCK_SUBSYS_CAN1 = 1 << 25,
STM32F10X_CLOCK_SUBSYS_CAN2 = 1 << 26,
STM32F10X_CLOCK_SUBSYS_BKP = 1 << 27,
STM32F10X_CLOCK_SUBSYS_PWR = 1 << 28,
STM32F10X_CLOCK_SUBSYS_DAC = 1 << 29,
STM32F10X_CLOCK_APB2_BASE = 1 << 31,
/* APB2 */
STM32F10X_CLOCK_SUBSYS_AFIO = STM32F10X_CLOCK_APB2_BASE | 1 << 0,
STM32F10X_CLOCK_SUBSYS_IOPA = STM32F10X_CLOCK_APB2_BASE | 1 << 2,
STM32F10X_CLOCK_SUBSYS_IOPB = STM32F10X_CLOCK_APB2_BASE | 1 << 3,
STM32F10X_CLOCK_SUBSYS_IOPC = STM32F10X_CLOCK_APB2_BASE | 1 << 4,
STM32F10X_CLOCK_SUBSYS_IOPD = STM32F10X_CLOCK_APB2_BASE | 1 << 5,
STM32F10X_CLOCK_SUBSYS_IOPE = STM32F10X_CLOCK_APB2_BASE | 1 << 6,
gpio: enable ports F G (and H) for stm32f1xx (stm32f4xx) Some GPIO ports activation where missing since not used on available soc/boards. Since stm32 family increases, activation of these ports should be made available. Jira: ZEP-1551 Change-Id: I612d135b28ef255bc771599e33796671ff81d0ac Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-02-20 18:34:00 +08:00
STM32F10X_CLOCK_SUBSYS_IOPF = STM32F10X_CLOCK_APB2_BASE | 1 << 7,
STM32F10X_CLOCK_SUBSYS_IOPG = STM32F10X_CLOCK_APB2_BASE | 1 << 8,
clock_control/stm32f10x: introduce driver for STM32F10x RCC The patch adds a driver for STM32F10x series RCC (Reset and Clock Control) subsystem. The module is primarily responsible for setting up of MCU's clock tree. In particular the driver sets up SYSCLK, PLL (with source configuration), AHB prescaler, and APB1/APB2 prescalers. As part of this functionality, the subsystem can enable/disable clock signal for particular peripherals, thus reducing the power consumption of the MCU. The driver implements clock control driver API. However, subsystem IDs being HW specific are exposed in driver public header that must be included by callers. The driver registers a single device using a common name STM32_CLOCK_CONTROL_NAME. The device is initialized at the PRIMARY level with priority 1. This allows the initialization to take place right after SoC initialization routine. The driver depends on selection of SOC_STM32F1X config option and is MCU specific. Change-Id: I8bea5db20726a24bce7b7ffe0b95de543240429a Origin: Original Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-03 22:33:04 +08:00
STM32F10X_CLOCK_SUBSYS_ADC1 = STM32F10X_CLOCK_APB2_BASE | 1 << 9,
STM32F10X_CLOCK_SUBSYS_ADC2 = STM32F10X_CLOCK_APB2_BASE | 1 << 10,
STM32F10X_CLOCK_SUBSYS_TIM1 = STM32F10X_CLOCK_APB2_BASE | 1 << 11,
STM32F10X_CLOCK_SUBSYS_SPI1 = STM32F10X_CLOCK_APB2_BASE | 1 << 12,
STM32F10X_CLOCK_SUBSYS_USART1 = STM32F10X_CLOCK_APB2_BASE | 1 << 14,
};
#endif /* _STM32F1_CLOCK_CONTROL_H_ */