2019-11-01 20:45:29 +08:00
|
|
|
# DesignWare SPI driver configuration options
|
|
|
|
|
2016-03-18 02:21:49 +08:00
|
|
|
# Copyright (c) 2015-2016 Intel Corporation
|
2017-01-19 09:01:01 +08:00
|
|
|
# SPDX-License-Identifier: Apache-2.0
|
2016-03-18 02:21:49 +08:00
|
|
|
|
2018-11-21 00:56:37 +08:00
|
|
|
config HAS_SPI_DW
|
|
|
|
bool
|
|
|
|
help
|
|
|
|
Signifies whether DesignWare SPI compatible HW is available
|
|
|
|
|
2016-03-18 02:21:49 +08:00
|
|
|
menuconfig SPI_DW
|
2017-06-21 15:16:25 +08:00
|
|
|
bool "Designware SPI controller driver"
|
2018-11-21 00:56:37 +08:00
|
|
|
depends on HAS_SPI_DW
|
2016-03-18 02:21:49 +08:00
|
|
|
help
|
|
|
|
Enable support for Designware's SPI controllers.
|
|
|
|
|
|
|
|
if SPI_DW
|
|
|
|
|
|
|
|
config SPI_DW_ARC_AUX_REGS
|
|
|
|
bool "Registers are part of ARC auxiliary registers"
|
2019-03-07 13:55:22 +08:00
|
|
|
depends on ARC
|
2016-03-18 02:21:49 +08:00
|
|
|
default y
|
|
|
|
help
|
|
|
|
SPI IP block registers are part of user extended auxiliary
|
|
|
|
registers and thus their access is different than memory
|
|
|
|
mapped registers.
|
|
|
|
|
2018-02-27 14:31:05 +08:00
|
|
|
config SPI_DW_FIFO_DEPTH
|
|
|
|
int "RX and TX FIFO Depth"
|
|
|
|
help
|
|
|
|
Corresponds to the SSI_TX_FIFO_DEPTH and
|
|
|
|
SSI_RX_FIFO_DEPTH of the DesignWare Synchronous
|
|
|
|
Serial Interface. Depth ranges from 2-256.
|
2016-03-18 02:21:49 +08:00
|
|
|
|
2019-09-10 12:00:15 +08:00
|
|
|
config SPI_DW_ACCESS_WORD_ONLY
|
|
|
|
bool "DesignWare SPI only allows word access"
|
|
|
|
help
|
|
|
|
In some case, e.g. ARC HS Development kit, the peripheral space of
|
|
|
|
DesignWare SPI only allows word access, byte access will raise
|
|
|
|
exception.
|
|
|
|
|
2016-03-18 02:21:49 +08:00
|
|
|
endif # SPI_DW
|