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zephyr/drivers/clock_control/clock_control_mcux_syscon.c

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drivers: Add NXP LPC clock control driver Add clock control driver for NXP LPC devices that use the MCUX SDK drivers Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-26 19:36:41 +08:00
/*
driver: clock: Update MCUX Syscon clock control driver 1. Update to add support for Flexcomm8-13. 2. Fix the clock control driver, the enclosing #define was incorrect. 3. Identify HS_SPI port using the appropriate Register define Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-08 01:36:17 +08:00
* Copyright (c) 2020-22, NXP
drivers: Add NXP LPC clock control driver Add clock control driver for NXP LPC devices that use the MCUX SDK drivers Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-26 19:36:41 +08:00
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_lpc_syscon
#include <errno.h>
#include <soc.h>
drivers: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all drivers to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to #45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 16:25:46 +08:00
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
drivers: Add NXP LPC clock control driver Add clock control driver for NXP LPC devices that use the MCUX SDK drivers Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-26 19:36:41 +08:00
#include <fsl_clock.h>
#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
drivers: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all drivers to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to #45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 16:25:46 +08:00
#include <zephyr/logging/log.h>
drivers: Add NXP LPC clock control driver Add clock control driver for NXP LPC devices that use the MCUX SDK drivers Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-26 19:36:41 +08:00
LOG_MODULE_REGISTER(clock_control);
static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
clock_control_subsys_t sub_system)
{
drivers: clock_control: lpc: syscon: add MCAN clock support Add support for the LPC MCAN clock to the LPC SYSCON clock controller driver. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-06-01 04:13:49 +08:00
#if defined(CONFIG_CAN_MCUX_MCAN)
uint32_t clock_name = (uint32_t)sub_system;
if (clock_name == MCUX_MCAN_CLK) {
CLOCK_EnableClock(kCLOCK_Mcan);
}
#endif /* defined(CONFIG_CAN_MCUX_MCAN) */
drivers: Add NXP LPC clock control driver Add clock control driver for NXP LPC devices that use the MCUX SDK drivers Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-26 19:36:41 +08:00
return 0;
}
static int mcux_lpc_syscon_clock_control_off(const struct device *dev,
clock_control_subsys_t sub_system)
{
return 0;
}
static int mcux_lpc_syscon_clock_control_get_subsys_rate(
const struct device *dev,
clock_control_subsys_t sub_system,
uint32_t *rate)
{
uint32_t clock_name = (uint32_t) sub_system;
switch (clock_name) {
driver: clock: Update MCUX Syscon clock control driver 1. Update to add support for Flexcomm8-13. 2. Fix the clock control driver, the enclosing #define was incorrect. 3. Identify HS_SPI port using the appropriate Register define Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-08 01:36:17 +08:00
drivers: clock_control: lpc: syscon: add MCAN clock support Add support for the LPC MCAN clock to the LPC SYSCON clock controller driver. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-06-01 04:13:49 +08:00
#if defined(CONFIG_I2C_MCUX_FLEXCOMM) || \
defined(CONFIG_SPI_MCUX_FLEXCOMM) || \
defined(CONFIG_UART_MCUX_FLEXCOMM)
drivers: Add NXP LPC clock control driver Add clock control driver for NXP LPC devices that use the MCUX SDK drivers Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-26 19:36:41 +08:00
case MCUX_FLEXCOMM0_CLK:
*rate = CLOCK_GetFlexCommClkFreq(0);
break;
case MCUX_FLEXCOMM1_CLK:
*rate = CLOCK_GetFlexCommClkFreq(1);
break;
case MCUX_FLEXCOMM2_CLK:
*rate = CLOCK_GetFlexCommClkFreq(2);
break;
case MCUX_FLEXCOMM3_CLK:
*rate = CLOCK_GetFlexCommClkFreq(3);
break;
case MCUX_FLEXCOMM4_CLK:
*rate = CLOCK_GetFlexCommClkFreq(4);
break;
case MCUX_FLEXCOMM5_CLK:
*rate = CLOCK_GetFlexCommClkFreq(5);
break;
case MCUX_FLEXCOMM6_CLK:
*rate = CLOCK_GetFlexCommClkFreq(6);
break;
case MCUX_FLEXCOMM7_CLK:
*rate = CLOCK_GetFlexCommClkFreq(7);
break;
driver: clock: Update MCUX Syscon clock control driver 1. Update to add support for Flexcomm8-13. 2. Fix the clock control driver, the enclosing #define was incorrect. 3. Identify HS_SPI port using the appropriate Register define Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-08 01:36:17 +08:00
case MCUX_FLEXCOMM8_CLK:
*rate = CLOCK_GetFlexCommClkFreq(8);
break;
case MCUX_FLEXCOMM9_CLK:
*rate = CLOCK_GetFlexCommClkFreq(9);
break;
case MCUX_FLEXCOMM10_CLK:
*rate = CLOCK_GetFlexCommClkFreq(10);
break;
case MCUX_FLEXCOMM11_CLK:
*rate = CLOCK_GetFlexCommClkFreq(11);
break;
case MCUX_FLEXCOMM12_CLK:
*rate = CLOCK_GetFlexCommClkFreq(12);
break;
case MCUX_FLEXCOMM13_CLK:
*rate = CLOCK_GetFlexCommClkFreq(13);
break;
dts: rt685: enabled flexcomm15 the RT685 contains an additional flexcomm peripheral, that supports only I2C. This commit adds this peripheral to the device tree, and enables pins and clocks for flexcomm15. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-09-22 03:12:23 +08:00
case MCUX_PMIC_I2C_CLK:
*rate = CLOCK_GetFlexCommClkFreq(15);
break;
drivers: Add NXP LPC clock control driver Add clock control driver for NXP LPC devices that use the MCUX SDK drivers Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-26 19:36:41 +08:00
case MCUX_HS_SPI_CLK:
driver: clock: Update MCUX Syscon clock control driver 1. Update to add support for Flexcomm8-13. 2. Fix the clock control driver, the enclosing #define was incorrect. 3. Identify HS_SPI port using the appropriate Register define Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-08 01:36:17 +08:00
#if defined(SYSCON_HSLSPICLKSEL_SEL_MASK)
drivers: Add NXP LPC clock control driver Add clock control driver for NXP LPC devices that use the MCUX SDK drivers Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-26 19:36:41 +08:00
*rate = CLOCK_GetHsLspiClkFreq();
#else
driver: clock: Update MCUX Syscon clock control driver 1. Update to add support for Flexcomm8-13. 2. Fix the clock control driver, the enclosing #define was incorrect. 3. Identify HS_SPI port using the appropriate Register define Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-08 01:36:17 +08:00
*rate = CLOCK_GetFlexCommClkFreq(14);
drivers: Add NXP LPC clock control driver Add clock control driver for NXP LPC devices that use the MCUX SDK drivers Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-26 19:36:41 +08:00
#endif
drivers: clock_control: mcux_lpc_syscon_clock: Add flexcomm16 suppport Added FlexCOMM16(HS SPI1) clock for MIMXRT5xx. Signed-off-by: Chay Guo <changyi.guo@nxp.com>
2022-05-16 16:23:23 +08:00
case MCUX_HS_SPI1_CLK:
*rate = CLOCK_GetFlexCommClkFreq(16);
drivers: Add NXP LPC clock control driver Add clock control driver for NXP LPC devices that use the MCUX SDK drivers Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-26 19:36:41 +08:00
break;
driver: clock: Update MCUX Syscon clock control driver 1. Update to add support for Flexcomm8-13. 2. Fix the clock control driver, the enclosing #define was incorrect. 3. Identify HS_SPI port using the appropriate Register define Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-08 01:36:17 +08:00
#endif
drivers: clock_control: Update LPC clock driver for USDHC Add support to get USDHC clock frequency Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2021-07-28 04:46:22 +08:00
#if (defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT)
case MCUX_USDHC1_CLK:
*rate = CLOCK_GetSdioClkFreq(0);
break;
case MCUX_USDHC2_CLK:
*rate = CLOCK_GetSdioClkFreq(1);
break;
drivers: counter: added ctimer driver for lpcexpresso55s69 Added shim driver for the CTIMERs for the lpcexpresso55s69 board. Fixes: #22705 Signed-off-by: Toby Firth <tobyjfirth@gmail.com>
2021-08-11 00:04:20 +08:00
#endif
driver: clock: Update MCUX Syscon clock control driver 1. Update to add support for Flexcomm8-13. 2. Fix the clock control driver, the enclosing #define was incorrect. 3. Identify HS_SPI port using the appropriate Register define Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-08 01:36:17 +08:00
drivers: clock_control: lpc: syscon: add MCAN clock support Add support for the LPC MCAN clock to the LPC SYSCON clock controller driver. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-06-01 04:13:49 +08:00
#if defined(CONFIG_CAN_MCUX_MCAN)
case MCUX_MCAN_CLK:
*rate = CLOCK_GetMCanClkFreq();
break;
#endif /* defined(CONFIG_CAN_MCUX_MCAN) */
driver: clock: Update MCUX Syscon clock control driver 1. Update to add support for Flexcomm8-13. 2. Fix the clock control driver, the enclosing #define was incorrect. 3. Identify HS_SPI port using the appropriate Register define Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-08 01:36:17 +08:00
drivers: counter: added ctimer driver for lpcexpresso55s69 Added shim driver for the CTIMERs for the lpcexpresso55s69 board. Fixes: #22705 Signed-off-by: Toby Firth <tobyjfirth@gmail.com>
2021-08-11 00:04:20 +08:00
#if defined(CONFIG_COUNTER_MCUX_CTIMER)
case (MCUX_CTIMER0_CLK + MCUX_CTIMER_CLK_OFFSET):
*rate = CLOCK_GetCTimerClkFreq(0);
break;
case (MCUX_CTIMER1_CLK + MCUX_CTIMER_CLK_OFFSET):
*rate = CLOCK_GetCTimerClkFreq(1);
break;
case (MCUX_CTIMER2_CLK + MCUX_CTIMER_CLK_OFFSET):
*rate = CLOCK_GetCTimerClkFreq(2);
break;
case (MCUX_CTIMER3_CLK + MCUX_CTIMER_CLK_OFFSET):
*rate = CLOCK_GetCTimerClkFreq(3);
break;
case (MCUX_CTIMER4_CLK + MCUX_CTIMER_CLK_OFFSET):
*rate = CLOCK_GetCTimerClkFreq(4);
break;
drivers: clock_control: Update LPC clock driver for USDHC Add support to get USDHC clock frequency Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2021-07-28 04:46:22 +08:00
#endif
drivers: clock_control: lpc: syscon: Add BUSCLK support Add support for the LPC BUS clock to the LPC SYSCON clock controller driver. Signed-off-by: Navin Sankar Velliangiri <navin@linumiz.com>
2022-03-09 02:22:17 +08:00
case MCUX_BUS_CLK:
*rate = CLOCK_GetFreq(kCLOCK_BusClk);
break;
drivers: Add NXP LPC clock control driver Add clock control driver for NXP LPC devices that use the MCUX SDK drivers Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-26 19:36:41 +08:00
}
return 0;
}
static int mcux_lpc_syscon_clock_control_init(const struct device *dev)
{
return 0;
}
static const struct clock_control_driver_api mcux_lpc_syscon_api = {
.on = mcux_lpc_syscon_clock_control_on,
.off = mcux_lpc_syscon_clock_control_off,
.get_rate = mcux_lpc_syscon_clock_control_get_subsys_rate,
};
#define LPC_CLOCK_INIT(n) \
\
drivers: clock_control: Convert drivers to new DT device macros Convert clock_control drivers from: DEVICE_AND_API_INIT -> DEVICE_DT{_INST}_DEFINE Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-12-16 02:20:28 +08:00
DEVICE_DT_INST_DEFINE(n, \
drivers: Add NXP LPC clock control driver Add clock control driver for NXP LPC devices that use the MCUX SDK drivers Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-26 19:36:41 +08:00
&mcux_lpc_syscon_clock_control_init, \
drivers: clock_control: remove usage of device_pm_control_nop device_pm_control_nop is now deprecated in favour of NULL. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-04-28 16:19:07 +08:00
NULL, \
drivers: Add NXP LPC clock control driver Add clock control driver for NXP LPC devices that use the MCUX SDK drivers Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-26 19:36:41 +08:00
NULL, NULL, \
drivers: clock_control: Refactor drivers to use shared init priority Refactors all of the clock control drivers to use a shared driver class initialization priority configuration, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, to allow configuring clock control drivers separately from other devices. This is similar to other driver classes like I2C and SPI. Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_OBJECTS or CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new option is the lower of the two, which means earlier initialization. The even lower defaults for STM32 and Arm Beetle are preserved by SoC-family level overrides. Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2021-10-19 03:45:17 +08:00
PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \
drivers: Add NXP LPC clock control driver Add clock control driver for NXP LPC devices that use the MCUX SDK drivers Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-26 19:36:41 +08:00
&mcux_lpc_syscon_api);
DT_INST_FOREACH_STATUS_OKAY(LPC_CLOCK_INIT)