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zephyr/drivers/spi/spi_dw_quark_se_ss_regs.h

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spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
/* spi_dw_quark_se_ss.h - Designware SPI driver private definitions */
/*
* Copyright (c) 2015 Intel Corporation.
*
license: Replace Apache boilerplate with SPDX tag Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 09:01:01 +08:00
* SPDX-License-Identifier: Apache-2.0
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
*/
#ifndef __SPI_DW_QUARK_SE_SS_H__
#define __SPI_DW_QUARK_SE_SS_H__
/* Registers:
* Some registers have been collapsed into one
* - SER is part of SSIENR
* - TXFTLR is part of RXFTLR
* This requires a little bit different access functions
* see below: write_ser(), write_rxftlr() and write_txftlr()
*/
#define DW_SPI_REG_CTRLR0 (0x00)
#define DW_SPI_REG_SSIENR (0x02)
#define DW_SPI_REG_BAUDR (0x04)
#define DW_SPI_REG_RXFTLR (0x05)
#define DW_SPI_REG_TXFLR (0x07)
#define DW_SPI_REG_RXFLR (0x08)
#define DW_SPI_REG_SR (0x09)
#define DW_SPI_REG_ISR (0x0a)
#define DW_SPI_REG_IMR (0x0b)
#define DW_SPI_REG_ICR (0x0c)
#define DW_SPI_REG_DR (0x0d)
#define DW_SPI_CTRLR0_CLK_ENA_BIT (15)
#define DW_SPI_CTRLR0_CLK_ENA_MASK BIT(DW_SPI_CTRLR0_CLK_ENA_BIT)
#define DW_SPI_QSS_SSIENR_SER(__slv) (__slv << 4)
#define DW_SPI_QSS_TXFTLR(__lvl) (__lvl << 16)
#define DW_SPI_QSS_SER_MASK (0xf0)
#define DW_SPI_QSS_RXFTLR_MASK (0x0000ffff)
#define DW_SPI_QSS_TXFTLR_MASK (0xffff0000)
#define DW_SPI_DR_WD_BIT (30)
#define DW_SPI_DR_WD_MASK BIT(DW_SPI_DR_WD_BIT)
#define DW_SPI_DR_STROBE_BIT (31)
#define DW_SPI_DR_STROBE_MASK BIT(DW_SPI_DR_STROBE_BIT)
#define DW_SPI_DR_WRITE (DW_SPI_DR_STROBE_MASK | \
DW_SPI_DR_WD_MASK)
#define DW_SPI_DR_READ (DW_SPI_DR_STROBE_MASK)
/* Register helpers
* *_b functions only used for creating proper ser one
*/
/* CTRLR0 on Quark SE SS has a CLK_ENA bit we want to keep
* as it is while writing the configuration.
* *_b function only used for creating proper ser one
*/
DEFINE_MM_REG_READ(ctrlr0_b, DW_SPI_REG_CTRLR0, 16)
DEFINE_MM_REG_WRITE(ctrlr0_b, DW_SPI_REG_CTRLR0, 16)
drivers: convert to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. Jira: ZEP-2051 Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 23:03:20 +08:00
static inline void write_ctrlr0(u32_t data, u32_t addr)
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
{
write_ctrlr0_b((read_ctrlr0_b(addr) & DW_SPI_CTRLR0_CLK_ENA_MASK) |
data, addr);
}
DEFINE_MM_REG_READ(ssienr_b, DW_SPI_REG_SSIENR, 8)
DEFINE_MM_REG_WRITE(ssienr_b, DW_SPI_REG_SSIENR, 8)
drivers: convert to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. Jira: ZEP-2051 Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 23:03:20 +08:00
static inline void write_ser(u32_t data, u32_t addr)
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
{
write_ssienr_b((read_ssienr_b(addr) & (~DW_SPI_QSS_SER_MASK)) |
DW_SPI_QSS_SSIENR_SER(data), addr);
}
DEFINE_MM_REG_READ(rxftlr_b, DW_SPI_REG_RXFTLR, 32)
DEFINE_MM_REG_WRITE(rxftlr_b, DW_SPI_REG_RXFTLR, 32)
DEFINE_MM_REG_READ(rxftlr, DW_SPI_REG_RXFTLR, 16)
drivers: convert to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. Jira: ZEP-2051 Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 23:03:20 +08:00
static inline void write_rxftlr(u32_t data, u32_t addr)
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
{
write_rxftlr_b((read_rxftlr_b(addr) & (~DW_SPI_QSS_RXFTLR_MASK)) |
data, addr);
}
drivers: convert to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. Jira: ZEP-2051 Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 23:03:20 +08:00
static inline void write_txftlr(u32_t data, u32_t addr)
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
{
write_rxftlr_b((read_rxftlr_b(addr) & (~DW_SPI_QSS_TXFTLR_MASK)) |
DW_SPI_QSS_TXFTLR(data), addr);
}
/* Quark SE SS requires to clear up all interrupts */
DEFINE_MM_REG_WRITE(icr, DW_SPI_REG_ICR, 8)
drivers: convert to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. Jira: ZEP-2051 Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 23:03:20 +08:00
static inline void clear_interrupts(u32_t addr)
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
{
write_icr(0x1f, addr);
}
/* Reading and Writing Data
* Quark SE SS DW SPI controller requires more logic from the driver which:
* - needs to tell when it has been pushing in bits for TX FIFO
* - needs to tell when it will be pulling out bits from RX FIFO
*/
DEFINE_MM_REG_WRITE(dr_b, DW_SPI_REG_DR, 32)
DEFINE_MM_REG_READ(dr_b, DW_SPI_REG_DR, 32)
drivers: convert to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. Jira: ZEP-2051 Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 23:03:20 +08:00
static inline void write_dr(u32_t data, u32_t addr)
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
{
write_dr_b(data | DW_SPI_DR_WRITE, addr);
}
drivers: convert to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. Jira: ZEP-2051 Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 23:03:20 +08:00
static inline u32_t read_dr(u32_t addr)
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
{
write_dr_b(DW_SPI_DR_READ, addr);
spi: dw: arc: add delay between writing DR strobe bit and reading FIFO According to documentation, there must be at least one cycle delay between two consecutive writes of the DR register. Apparently, this is true for reading too, though undocumented. The read_dr() inline function is called as follows: *(spi->rx_buf) = read_dr(info->regs); which the compiler, with full optimizations on, turns it into: ld_s r2,[r1,24] <- the spi->rx_buf sr 0x80000000,[r4] <- this is the strobe bit write !!! lr r4,[r4] <- this is the FIFO read!!! stb r4,[r2] <- store the result Unfortunately, the read from the FIFO is always 0 since the FIFO data is not yet available. During my investigations, I found that the following code works: sys_out32(1 << 31, info->regs + 0xd); *(spi->rx_buf) = sys_in32(info->regs + 0xd); This does, basically, the same thing. But the compiler inserts an instruction in between the write/read: sr 0x80000000,[r4] <- write of the strobe bit!!! ld_s r2,[r1,24] <- the pointer goes to r2 lr r4,[r4] <- read from FIFO!!! stb r4,[r2] <- store the result A single clock cycle between writing the register and reading seems to be enough for the data to become available for reading. This patch adds a nop in the read_dr() inline function. Change-Id: I0c216d5738d5771835b1052e2e83363e8e3abf0c Signed-off-by: Laurentiu Palcu <laurentiu.palcu@intel.com>
2016-03-10 17:25:03 +08:00
__asm__("nop\n");
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
return read_dr_b(addr);
}
/* Internal clock gating */
DEFINE_SET_BIT_OP(clk_ena, DW_SPI_REG_CTRLR0, DW_SPI_CTRLR0_CLK_ENA_BIT)
DEFINE_CLEAR_BIT_OP(clk_ena, DW_SPI_REG_CTRLR0, DW_SPI_CTRLR0_CLK_ENA_BIT)
#define _clock_config(...)
static inline void _clock_on(struct device *dev)
{
spi/dw: Make config_info pointers const. Make pointers to struct config_info const in prepration for a const config_info. Change-Id: I28789a7f1f26e4a0d499f5a89a567ae8c61eae51 Signed-off-by: Marcus Shawcroft <marcus.shawcroft@gmail.com>
2016-10-07 02:28:52 +08:00
const struct spi_dw_config *info = dev->config->config_info;
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
set_bit_clk_ena(info->regs);
}
static inline void _clock_off(struct device *dev)
{
spi/dw: Make config_info pointers const. Make pointers to struct config_info const in prepration for a const config_info. Change-Id: I28789a7f1f26e4a0d499f5a89a567ae8c61eae51 Signed-off-by: Marcus Shawcroft <marcus.shawcroft@gmail.com>
2016-10-07 02:28:52 +08:00
const struct spi_dw_config *info = dev->config->config_info;
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
clear_bit_clk_ena(info->regs);
}
#endif /* __SPI_DW_QUARK_SE_SS_H__ */