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zephyr/soc/soc_legacy/riscv/litex_vexriscv/Kconfig.soc

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soc: riscv32: add LiteX VexRiscV SoC Add LiteX with softcore CPU VexRiscV SoC definitions and default configurations. Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2019-03-28 21:47:16 +08:00
# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_RISCV32_LITEX_VEXRISCV
bool "LiteX VexRiscv system implementation"
kconfig: Remove assignments to CONFIG_<arch> syms and hide them All board defconfig files currently set the architecture in addition to the board and the SoC, by setting e.g. CONFIG_ARM=y. This spams up defconfig files. CONFIG_<arch> symbols currently being set in configuration files also means that they are configurable (can be changed in menuconfig and in configuration files), even though changing the architecture won't work, since other things get set from -DBOARD=<board>. Many boards also allow changing the architecture symbols independently from the SoC symbols, which doesn't make sense. Get rid of all assignments to CONFIG_<arch> symbols and clean up the relationships between symbols and the configuration interface, like this: 1. Remove the choice with the CONFIG_<arch> symbols in arch/Kconfig and turn the CONFIG_<arch> symbols into invisible (promptless/nonconfigurable) symbols instead. Getting rid of the choice allows the symbols to be 'select'ed (choice symbols don't support 'select'). 2. Select the right CONFIG_<arch> symbol from the SOC_SERIES_* symbols. This makes sense since you know the architecture if you know the SoC. Put the select on the SOC_* symbol instead for boards that don't have a SOC_SERIES_*. 3. Remove all assignments to CONFIG_<arch> symbols. The assignments would generate errors now, since the symbols are promptless. The change was done by grepping for assignments to CONFIG_<arch> symbols, finding the SOC_SERIES_* (or SOC_*) symbol being set in the same defconfig file, and putting a 'select' on it instead. See https://github.com/ulfalizer/zephyr/commits/hide-arch-syms-unsquashed for a split-up version of this commit, which will make it easier to see how stuff was done. This needs to go in as one commit though. This change is safer than it might seem re. outstanding PRs, because any assignment to CONFIG_<arch> symbols generates an error now, making outdated stuff easy to catch. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-02-07 01:26:14 +08:00
select RISCV
soc: riscv32: add LiteX VexRiscV SoC Add LiteX with softcore CPU VexRiscV SoC definitions and default configurations. Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2019-03-28 21:47:16 +08:00
select ATOMIC_OPERATIONS_C
soc: riscv: priv: call __reset during boot Call __reset instead of directly calling __initialize from the common RISC-V privileged SoC vectors __start. This allows injection of SoC specific reset code just after setting up the machine trap vector. RISC-V privilege SoCs without the need for custom reset code can set CONFIG_INCLUDE_RESET_VECTOR=y to include a __reset stub which simply calls __initialize. Fixes: #38396 Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-09-09 04:20:10 +08:00
select INCLUDE_RESET_VECTOR
riscv: Rework and cleanup Kconfig This patch is doing several things: - Core ISA and extension Kconfig symbols have now a formalized name (CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*) - a new Kconfig.isa file was introduced with the full set of extensions currently supported by the v2.2 spec - a new Kconfig.core file was introduced to host all the RISCV cores (currently only E31) - ISA and extensions settings are moved to SoC configuration files Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-05-12 18:03:47 +08:00
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
riscv: Introduce Zicsr and Zifencei extensions And enable the new extensions on all the SoCs. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-06-13 23:21:35 +08:00
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
soc: litex-vexriscv: Implement universal LiteX HAL Adds LITEX_CSR_DATA_WIDTH option to Kconfig Depending on its value appropriate read/write handling is used for accessing CSR registers. By using `>=` in preprocessor conditions it is somewhat future-proofed. Doesn't touch `litex_read` and `litex_write` yet. Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
2022-04-07 20:14:04 +08:00
if SOC_RISCV32_LITEX_VEXRISCV
config LITEX_CSR_DATA_WIDTH
int "Select Control/Status register width"
default 32
endif # SOC_RISCV32_LITEX_VEXRISCV