109 lines
2.0 KiB
Plaintext
109 lines
2.0 KiB
Plaintext
|
# Kconfig - ADC configuration options
|
||
|
|
|
||
|
|
#
|
||
|
|
# Copyright (c) 2015 Intel Corporation
|
||
|
|
#
|
||
|
|
# SPDX-License-Identifier: Apache-2.0
|
||
|
|
#
|
||
|
|
|
||
|
|
menuconfig ADC_DW
|
||
|
|
bool "ARC Designware Driver"
|
||
|
|
depends on ARC
|
||
|
|
select ADC_0
|
||
|
|
help
|
||
|
|
Enable the driver implementation of the Designware ADC IP.
|
||
|
|
|
||
|
|
if ADC_DW
|
||
|
|
|
||
|
|
|
||
|
|
config ADC_DW_CALIBRATION
|
||
|
|
bool "Enable Calibration"
|
||
|
|
default y
|
||
|
|
help
|
||
|
|
Enables ADC to run with a calibrated output at the
|
||
|
|
expense of execution speed when exiting low power states.
|
||
|
|
If disabled, the ADC will require the application/system-integrator
|
||
|
|
to provide a calibration method.
|
||
|
|
|
||
|
|
config ADC_DW_DUMMY_CONVERSION
|
||
|
|
bool "Enable dummy conversion"
|
||
|
|
default y
|
||
|
|
help
|
||
|
|
After awaking from low power state a dummy
|
||
|
|
conversion must be performed and discarded.
|
||
|
|
If disabled the user will have to discard the first
|
||
|
|
sample after a resume from a low power state.
|
||
|
|
|
||
|
|
choice
|
||
|
|
prompt "Output Mode"
|
||
|
|
default ADC_DW_SERIAL
|
||
|
|
help
|
||
|
|
ADC output mode: parallel or serial.
|
||
|
|
|
||
|
|
config ADC_DW_SERIAL
|
||
|
|
bool "Serial"
|
||
|
|
|
||
|
|
config ADC_DW_PARALLEL
|
||
|
|
bool "Parallel"
|
||
|
|
|
||
|
|
endchoice
|
||
|
|
|
||
|
|
choice
|
||
|
|
prompt "Sequence Mode"
|
||
|
|
default ADC_DW_SINGLESHOT
|
||
|
|
help
|
||
|
|
ADC sequence mode - single run/repetitive
|
||
|
|
|
||
|
|
config ADC_DW_SINGLESHOT
|
||
|
|
bool "Single Ended"
|
||
|
|
|
||
|
|
config ADC_DW_REPETITIVE
|
||
|
|
bool "Differential"
|
||
|
|
|
||
|
|
endchoice
|
||
|
|
|
||
|
|
choice
|
||
|
|
prompt "Capture Mode"
|
||
|
|
default ADC_DW_RISING_EDGE
|
||
|
|
help
|
||
|
|
ADC controller capture mode:
|
||
|
|
by rising or falling edge of adc_clk
|
||
|
|
|
||
|
|
config ADC_DW_RISING_EDGE
|
||
|
|
bool "Rising Edge"
|
||
|
|
|
||
|
|
config ADC_DW_FALLING_EDGE
|
||
|
|
bool "Falling Edge"
|
||
|
|
|
||
|
|
endchoice
|
||
|
|
|
||
|
|
config ADC_DW_SAMPLE_WIDTH
|
||
|
|
int "Sample Width"
|
||
|
|
default 31
|
||
|
|
help
|
||
|
|
Defines ADC device data sample width (resolution):
|
||
|
|
|
||
|
|
- 0 = 6 bits resolution
|
||
|
|
|
||
|
|
- 1 = 8 bits resolution
|
||
|
|
|
||
|
|
- 2 = 10 bits resolution
|
||
|
|
|
||
|
|
- 3 = 12 bits resolution
|
||
|
|
|
||
|
|
config ADC_DW_SERIAL_DELAY
|
||
|
|
int "Serial Delay"
|
||
|
|
default 1
|
||
|
|
help
|
||
|
|
Number of ADC clock ticks that the first bit of
|
||
|
|
the serial output is delayed after the conversion
|
||
|
|
has started.
|
||
|
|
|
||
|
|
config ADC_DW_CLOCK_RATIO
|
||
|
|
int "Clock Ratio"
|
||
|
|
default 1024
|
||
|
|
help
|
||
|
|
ADC Clock Ratio
|
||
|
|
|
||
|
|
endif # ADC_DW
|