zephyr/soc/xlnx/zynqmp/soc.h

/*
 * Copyright (c) 2019 Lexmark International, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 */

#ifndef _BOARD__H_
#define _BOARD__H_

/* Define CMSIS configurations */
#define __CR_REV		1U

#endif /* _BOARD__H_ */
soc: arm: xilinx_zynqmp: Add qemu based SoC This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <bbolen@lexmark.com> 2019-07-22 22:23:47 +08:00			`/*`
			`* Copyright (c) 2019 Lexmark International, Inc.`
			`*`
			`* SPDX-License-Identifier: Apache-2.0`
			`*`
			`*/`

			`#ifndef _BOARD__H_`
			`#define _BOARD__H_`

soc: arm: xilinx_zynqmp: Use CMSIS-Core(R) This commit updates the `xilinx_zynqmp` SoC initialisation code to use the CMSIS-Core(R) features. In addition, it also defines the Core IP revision value for the SoC as specified in the Zynq UltraScale+ Device Technical Reference Manual. Signed-off-by: Stephanos Ioannidis <root@stephanos.io> 2020-02-12 13:48:21 +08:00			`/* Define CMSIS configurations */`
			`#define __CR_REV 1U`
soc: arm: xilinx_zynqmp: Add qemu based SoC This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <bbolen@lexmark.com> 2019-07-22 22:23:47 +08:00
			`#endif /* _BOARD__H_ */`