2019-01-23 18:31:32 +08:00
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/*
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* Copyright (c) 2019 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2019-06-16 19:17:06 +08:00
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#include <xtensa/xtensa.dtsi>
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2019-01-23 18:31:32 +08:00
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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2019-06-21 20:47:08 +08:00
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cpu0: cpu@0 {
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2019-01-23 18:31:32 +08:00
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device_type = "cpu";
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2019-06-16 18:28:57 +08:00
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compatible = "cadence,tensilica-xtensa-lx6";
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2019-01-23 18:31:32 +08:00
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reg = <0>;
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};
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2019-06-21 20:47:08 +08:00
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cpu1: cpu@1 {
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2019-01-23 18:31:32 +08:00
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device_type = "cpu";
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2019-06-16 18:28:57 +08:00
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compatible = "cadence,tensilica-xtensa-lx6";
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2019-01-23 18:31:32 +08:00
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reg = <1>;
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};
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};
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sram0: memory@3ffb0000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x3FFB0000 0x50000>;
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};
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soc {
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uart0: uart@40008fd0 {
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2019-06-16 19:17:06 +08:00
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compatible = "espressif,esp32-uart";
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2019-01-23 18:31:32 +08:00
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reg = <0x40008fd0 0x400>;
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label = "ROMUART";
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status = "disabled";
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};
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};
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};
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