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zephyr/arch/x86/soc/quark_se/Kconfig

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x86: add support for the Quark SE platform Intel Quark SE Microcontroller with an onboard sensor subsystem. Processor * Intel Quark SE Processor Core * Intel Pentium® Processor-based x86 ISA compatible CPU * 32MHz clock, 32-bit address bus * 8kB 2-way L1 instruction cache Memory * 384kB of on-die NVM +8kB OTP on-die NVM * 80kB of on-die SRAM Change-Id: I849ec5c1f1639e10a48c9ebab7d3653b88b23eb7 Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-11-22 11:25:41 +08:00
# Kconfig - Quark SE configuration options
#
kconfig: untangle ordering and dependencies There are two major issues with the kconfig: () Some of the config options have incorrect dependencies inside help under menuconfig. For example, CONFIG_GPIO depends on BOARD_GALILEO. () Since the SoC and board specific kconfig files are parsed first, the help screen would say, for example, CONFIG_SPI is defined at arch/arm/soc/fsl_frdm_k64f/Kconfig. This is incorrect because the actual config is defined in drivers/spi/Kconfig. These cause great confusion to users of menuconfig/xconfig. To fix these, the SoC and board defaults are now to be parsed last. Note that the position swapping of defaults in this patch is due to the fact the the default parsed last will be used. And, spi_test is broken due to the fact that it requires CONFIG_SPI_INTEL_PORT_1, but never enables it anywhere. This is bypassed for now. Origin: refactored and edited from existing files Change-Id: I2a4b1ae5be4d27e68c960aa47d91ef350f2d500f Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-26 05:30:50 +08:00
# Copyright (c) 2016 Intel Corporation
x86: add support for the Quark SE platform Intel Quark SE Microcontroller with an onboard sensor subsystem. Processor * Intel Quark SE Processor Core * Intel Pentium® Processor-based x86 ISA compatible CPU * 32MHz clock, 32-bit address bus * 8kB 2-way L1 instruction cache Memory * 384kB of on-die NVM +8kB OTP on-die NVM * 80kB of on-die SRAM Change-Id: I849ec5c1f1639e10a48c9ebab7d3653b88b23eb7 Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-11-22 11:25:41 +08:00
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
kconfig: untangle ordering and dependencies There are two major issues with the kconfig: () Some of the config options have incorrect dependencies inside help under menuconfig. For example, CONFIG_GPIO depends on BOARD_GALILEO. () Since the SoC and board specific kconfig files are parsed first, the help screen would say, for example, CONFIG_SPI is defined at arch/arm/soc/fsl_frdm_k64f/Kconfig. This is incorrect because the actual config is defined in drivers/spi/Kconfig. These cause great confusion to users of menuconfig/xconfig. To fix these, the SoC and board defaults are now to be parsed last. Note that the position swapping of defaults in this patch is due to the fact the the default parsed last will be used. And, spi_test is broken due to the fact that it requires CONFIG_SPI_INTEL_PORT_1, but never enables it anywhere. This is bypassed for now. Origin: refactored and edited from existing files Change-Id: I2a4b1ae5be4d27e68c960aa47d91ef350f2d500f Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-26 05:30:50 +08:00
if X86 && SOC_QUARK_SE
x86: add support for the Quark SE platform Intel Quark SE Microcontroller with an onboard sensor subsystem. Processor * Intel Quark SE Processor Core * Intel Pentium® Processor-based x86 ISA compatible CPU * 32MHz clock, 32-bit address bus * 8kB 2-way L1 instruction cache Memory * 384kB of on-die NVM +8kB OTP on-die NVM * 80kB of on-die SRAM Change-Id: I849ec5c1f1639e10a48c9ebab7d3653b88b23eb7 Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-11-22 11:25:41 +08:00
quark_se: apic: work around EOI forwarding issue Quark SE Lakemont core has a hardware bug where the LOAPIC does not properly notify the IOAPIC to clear the IRR bit for level- triggered interrupts. This patch introduces a workaround where the vector ID of the in-service interrupt is manually written to the IOAPIC_EOI register, resulting in the bit being cleared. Unfortunately, in the context where EOI happens it's very difficult to identify which IRQ line is being serviced, so this is done unconditionally for all interrupts vectors whether they are registered in the IOAPIC RTE table or not. Change-Id: I639cd258dec4f50934e17eadbb821e6a7112e636 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-12-11 06:43:10 +08:00
config EOI_FORWARDING_BUG
bool
default y
help
Quark SE LOAPIC has issues with forwarding EOI to the IOAPIC for level
triggered interrupts, this is a SW workaround.
quark_se: remove hardcoded reset vector for ARC Change-Id: Iba4d46b50990167aa9e21635a6a8e6c1dd90c5e3 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-29 06:49:43 +08:00
config SS_RESET_VECTOR
hex "Sensor Subsystem Reset Vector"
default 0x40000000
help
Sensor subsystem reset vector. This value is needed to init the ARC
system on the SoC.
x86: add support for the Quark SE platform Intel Quark SE Microcontroller with an onboard sensor subsystem. Processor * Intel Quark SE Processor Core * Intel Pentium® Processor-based x86 ISA compatible CPU * 32MHz clock, 32-bit address bus * 8kB 2-way L1 instruction cache Memory * 384kB of on-die NVM +8kB OTP on-die NVM * 80kB of on-die SRAM Change-Id: I849ec5c1f1639e10a48c9ebab7d3653b88b23eb7 Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-11-22 11:25:41 +08:00
config ARC_INIT
bool "Quark SE ARC Kickoff"
default n
help
Allows x86 processor to kickoff the ARC slave processor.
sys_log: replace old debug macros at SSS boot The boot initialization and boot process of the sensor sub systems is now using the new system log macros and updated the Kconfig variable to be a level rather than a bool. Change-Id: I098143684f8e7077a525e7fcbc93b42b22d427ac Signed-off-by: Genaro Saucedo Tejada <genaro.saucedo.tejada@intel.com>
2016-07-30 04:27:29 +08:00
config SYS_LOG_ARC_INIT_LEVEL
int
prompt "Quark SE Sensor Subsystem log level"
default 0
add a new option for debugging quark se We had wrong logic and confusing config options for debugging Quark SE sensor subsystem. The new option will be used for GDB debugging. The existing DEBUG option will be used for printing additional messages on the screen while booting the sensor sub-system. Change-Id: Ia54d22e872edafe531ccde271e7504fe9c48a73a Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-12 05:40:01 +08:00
help
sys_log: replace old debug macros at SSS boot The boot initialization and boot process of the sensor sub systems is now using the new system log macros and updated the Kconfig variable to be a level rather than a bool. Change-Id: I098143684f8e7077a525e7fcbc93b42b22d427ac Signed-off-by: Genaro Saucedo Tejada <genaro.saucedo.tejada@intel.com>
2016-07-30 04:27:29 +08:00
Sets log level for the boot initialization and boot process of the sensor
add a new option for debugging quark se We had wrong logic and confusing config options for debugging Quark SE sensor subsystem. The new option will be used for GDB debugging. The existing DEBUG option will be used for printing additional messages on the screen while booting the sensor sub-system. Change-Id: Ia54d22e872edafe531ccde271e7504fe9c48a73a Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-12 05:40:01 +08:00
sub-system.
sys_log: replace old debug macros at SSS boot The boot initialization and boot process of the sensor sub systems is now using the new system log macros and updated the Kconfig variable to be a level rather than a bool. Change-Id: I098143684f8e7077a525e7fcbc93b42b22d427ac Signed-off-by: Genaro Saucedo Tejada <genaro.saucedo.tejada@intel.com>
2016-07-30 04:27:29 +08:00
Levels are:
- 0 OFF, do not write
- 1 ERROR, only write SYS_LOG_ERR
- 2 WARNING, write SYS_LOG_WRN in adition to previous level
- 3 INFO, write SYS_LOG_INF in adition to previous levels
- 4 DEBUG, write SYS_LOG_DBG in adition to previous levels
add a new option for debugging quark se We had wrong logic and confusing config options for debugging Quark SE sensor subsystem. The new option will be used for GDB debugging. The existing DEBUG option will be used for printing additional messages on the screen while booting the sensor sub-system. Change-Id: Ia54d22e872edafe531ccde271e7504fe9c48a73a Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-12 05:40:01 +08:00
config ARC_GDB_ENABLE
x86: add support for the Quark SE platform Intel Quark SE Microcontroller with an onboard sensor subsystem. Processor * Intel Quark SE Processor Core * Intel Pentium® Processor-based x86 ISA compatible CPU * 32MHz clock, 32-bit address bus * 8kB 2-way L1 instruction cache Memory * 384kB of on-die NVM +8kB OTP on-die NVM * 80kB of on-die SRAM Change-Id: I849ec5c1f1639e10a48c9ebab7d3653b88b23eb7 Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-11-22 11:25:41 +08:00
bool "Allows the usage of GDB with the ARC processor."
depends on ARC_INIT
default n
help
This option will stop the master processor from boot-strapping
the ARC slave processor. This will allow GDB to halt and
engage the ARC processor to proceed step by step execution.
quark_se: increase IPM buffer size and make it configurable The original value of 128 was selected more or less randomly, and isn't sufficiently large enough for QA needs. Change-Id: I8a9fcc86d6b5fa7dc5ba05896c62f7dd608f9ed2 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-01-21 03:42:12 +08:00
if IPM_CONSOLE_RECEIVER
config QUARK_SE_IPM_CONSOLE_RING_BUF_SIZE32
build: make QUARK_SE_IPM_CONSOLE_RING_BUF_SIZE32 symbol editable QUARK_SE_IPM_CONSOLE_RING_BUF_SIZE32 symbol must be editable through configuration menus and configuration snippets (QA request). Adding a title for the kconfig symbol makes it editable. Change-Id: Id0147a50d94033e1392327935bcbfbdb5a9eedd8 Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-01-30 02:37:28 +08:00
int "IPM Console Ring Buffer Size"
quark_se: increase IPM buffer size and make it configurable The original value of 128 was selected more or less randomly, and isn't sufficiently large enough for QA needs. Change-Id: I8a9fcc86d6b5fa7dc5ba05896c62f7dd608f9ed2 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-01-21 03:42:12 +08:00
default 256
help
Size of the buffer for the console reciever, for incoming
console messages from the ARC side. Must be a power of 2.
endif
Use SoC instead of platform. Change terminology and use SoC instead of platform. An SoC provides features and default configurations available with an SoC. A board implements the SoC and adds more features and IP block specific to the board to extend the SoC functionality such as sensors and debugging features. Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-12-17 21:54:35 +08:00
endif #SOC_QUARK_SE_X86