OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/drivers/interrupt_controller/Kconfig

87 lines
2.3 KiB
Plaintext
Raw Normal View History

kconfig: Clean up header comments and make them consistent Use this short header style in all Kconfig files: # <description> # <copyright> # <license> ... Also change all <description>s from # Kconfig[.extension] - Foo-related options to just # Foo-related options It's clear enough that it's about Kconfig. The <description> cleanup was done with this command, along with some manual cleanup (big letter at the start, etc.) git ls-files '*Kconfig*' | \ xargs sed -i -E '1 s/#\s*Kconfig[\w.-]*\s*-\s*/# /' Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-11-01 20:45:29 +08:00
# interrupt controller configuration options
x86/bsp: move PIC (i8259) driver to drivers/interrupt_controller Change-Id: I383424667f291ad4985781a7e6566c01c76ba5e0 Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-15 21:20:24 +08:00
# Copyright (c) 2015 Intel Corporation
license: Replace Apache boilerplate with SPDX tag Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 09:01:01 +08:00
# SPDX-License-Identifier: Apache-2.0
x86/bsp: move PIC (i8259) driver to drivers/interrupt_controller Change-Id: I383424667f291ad4985781a7e6566c01c76ba5e0 Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-15 21:20:24 +08:00
menu "Interrupt Controllers"
arc: move interrupt controller to drivers/ Change-Id: I731c99062f4b5d2d4d1eb6a3c546ed5f3e494fa4 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-06-20 21:26:06 +08:00
config ARCV2_INTERRUPT_UNIT
bool "ARCv2 Interrupt Unit"
default y
depends on ARC
help
kconfig: fix help syntax and add spaces Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-13 23:08:21 +08:00
The ARCv2 interrupt unit has 16 allocated exceptions associated with
vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255.
The interrupt unit is optional in the ARCv2-based processors. When
building a processor, you can configure the processor to include an
interrupt unit. The ARCv2 interrupt unit is highly programmable.
interupt_controller/stm32_exti: driver for STM32 EXTI controller Introcuce a driver for External Interrupt/Event Controller (EXTI) found on STM32 MCUs. Change-Id: Ib206521fcc51b5dfaaf5dea9d436f8304f3a36be Origin: Original Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-14 23:29:46 +08:00
drivers: interrupt_controller: Add SweRV PIC support Add support for the built-in Programmable Interrupt Controller found in the SweRV EH1 RISC-V CPU Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
2019-10-10 19:51:18 +08:00
config SWERV_PIC
bool "SweRV EH1 Programmable Interrupt Controller (PIC)"
drivers: intc: Update drivers to use devicetree Kconfig symbol Update intc drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol to expose the driver and enable it by default based on devicetree. We remove 'depend on' Kconfig for symbols that would be implied by the devicetree node existing. Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-22 14:46:51 +08:00
default y
depends on DT_HAS_SWERV_PIC_ENABLED
drivers: interrupt_controller: Add SweRV PIC support Add support for the built-in Programmable Interrupt Controller found in the SweRV EH1 RISC-V CPU Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
2019-10-10 19:51:18 +08:00
help
Kconfig: Introduce RISCV_HAS_CLIC Introduce a new RISCV_HAS_CLIC symbol for platforms using CLIC, reorganize the Kconfigs and make the Nuclei ECLIC depending on the new symbol. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-07 22:27:17 +08:00
Programmable Interrupt Controller for the SweRV EH1 RISC-V CPU.
drivers: interrupt_controller: Add SweRV PIC support Add support for the built-in Programmable Interrupt Controller found in the SweRV EH1 RISC-V CPU Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
2019-10-10 19:51:18 +08:00
drivers: interrupt_controller: add LiteX interrupt controller driver Add LiteX interrupt controller driver and bindings for this device. Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2019-03-28 21:44:12 +08:00
config VEXRISCV_LITEX_IRQ
bool "VexRiscv LiteX Interrupt controller"
drivers: intc: Update drivers to use devicetree Kconfig symbol Update intc drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol to expose the driver and enable it by default based on devicetree. We remove 'depend on' Kconfig for symbols that would be implied by the devicetree node existing. Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-22 14:46:51 +08:00
default y
depends on DT_HAS_VEXRISCV_INTC0_ENABLED
drivers: interrupt_controller: add LiteX interrupt controller driver Add LiteX interrupt controller driver and bindings for this device. Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2019-03-28 21:44:12 +08:00
help
IRQ implementation for LiteX VexRiscv
intc: Add support for GRLIB IRQMP This adds support for the GRLIB IRQMP interrupt controller commonly used in LEON3/4/5 systems. The driver supports the 15 SPARC interrupts and 16 extended interrupts. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-10-17 02:57:21 +08:00
config LEON_IRQMP
bool "GRLIB IRQMP interrupt controller"
default y
drivers: intc: Update drivers to use devicetree Kconfig symbol Update intc drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol to expose the driver and enable it by default based on devicetree. We remove 'depend on' Kconfig for symbols that would be implied by the devicetree node existing. Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-22 14:46:51 +08:00
depends on DT_HAS_GAISLER_IRQMP_ENABLED
intc: Add support for GRLIB IRQMP This adds support for the GRLIB IRQMP interrupt controller commonly used in LEON3/4/5 systems. The driver supports the 15 SPARC interrupts and 16 extended interrupts. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-10-17 02:57:21 +08:00
help
GRLIB IRQMP and IRQAMP
drivers: interrupt_controller: Refactor drivers to use shared init prio Refactors interrupt controller drivers to use the shared driver class initialization priority configuration, CONFIG_INTC_INIT_PRIORITY, to allow configuring interrupt controller drivers separately from other devices. This is similar to other driver classes. The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEFAULT to preserve the existing default initialization priority for most drivers. Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2022-03-12 06:25:41 +08:00
config INTC_INIT_PRIORITY
int "Interrupt controller init priority"
default KERNEL_INIT_PRIORITY_DEFAULT
help
Interrupt controller device initialization priority.
ITE drivers/interrupt_controller: add wuc interface Add wakeup controller interface for ITE it8xxx2 chip. Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-09-07 13:45:39 +08:00
module = INTC
module-str = intc
source "subsys/logging/Kconfig.template.log_config"
drivers/interrupt_controller: Introduce multi-level interrupt support In a scenario where a platform harbours multiple interrupts to the extent the core cannot support it, an interrupt controller is added as an additional level of interrupt. It typically combines several sources of interrupt into one line that is then routed to the parent controller. Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2017-12-24 17:48:57 +08:00
source "drivers/interrupt_controller/Kconfig.multilevel"
drivers/interrupt_controller: Split Kconfig for clarity Let's move loapic and dw related options into there own Kconfig file. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2019-12-18 16:42:14 +08:00
source "drivers/interrupt_controller/Kconfig.loapic"
source "drivers/interrupt_controller/Kconfig.dw"
drivers/interrupt: it8xxx2 driver interrupt-control This commit is about platform it8xxx2 interrupt. The interrupt irqs should reference the datasheet. Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
2020-09-09 11:36:28 +08:00
source "drivers/interrupt_controller/Kconfig.it8xxx2"
drivers/interrupt_controller: Split Kconfig for clarity Let's move loapic and dw related options into there own Kconfig file. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2019-12-18 16:42:14 +08:00
source "drivers/interrupt_controller/Kconfig.stm32"
drivers/interrupt_controller: Renaming s1000 to cavs If it is such a thing (a CAVT intc), it will not be targeting Intel s1000 SoC only. UP squarde ADSP use the same intc. So renaming it to CAVS. Though CAVS name might be wrong (CAVS being an overall architecture name, and not an IP block specification). Reducing the amount of lines by using if/endif as well. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2019-12-18 16:48:56 +08:00
source "drivers/interrupt_controller/Kconfig.cavs"
drivers: interrupts: introduce CAVS interrupt logic CAVS interrupt logic is an intel IP that combines several sources of interrupt into one line that is then routed to the parent controller. CAVS stands for "connected Audio, Voice and Speech". This IP supports 4 lines which can have a max of 32 interrupts each. Change-Id: Ia6be51428bedf1011d148ae1fc5d4c34252c05da Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-12 01:06:20 +08:00
interrupt_controller: RV32M1: add intmux driver / DT bindings Add a level 2 interrupt controller for the RV32M1 SoC. This uses the INTMUX peripheral. As a first customer, convert the timer driver over to using this, adding nodes for the LPTMR peripherals. This lets users select the timer instance they want to use, and what intmux channel they want to route its interrupt to, using DT overlays. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Mike Scott <mike@foundries.io>
2018-11-25 17:41:38 +08:00
source "drivers/interrupt_controller/Kconfig.rv32m1"
drivers: gpio: sam0: Add interrupt support This adds interrupt support to the SAM0 GPIO driver. This is heavily inspired by @nzmichaelh work in #5715. The primary difference from that implementation is that here the External Interrupt Controller (EIC) is separated out into an interrupt controller driver that is less tightly coupled to the GPIO API. Instead it implements more of a conversion from the EIC's own odd multiplexing to a more traditional port and pin mask IRQ-like callback. Unfortunately, through the EIC on the SAMD2x are relatively well behaved in terms of pin to EIC line mappings, other chips that share the peripheral interface are not. So the EIC driver implements a per-line lookup to the pin and port pair using definitions extracted from the ASF headers. The EIC driver still makes some assumptions about how it will be used: mostly it assumes exactly one callback per port. This should be fine as the only intended user is the GPIO driver itself. This has been tested with some simple programs and with tests/drivers/gpio/gpio_basic_api on a SAMD21 breakout and an adafruit_trinket_m0 board. Signed-off-by: Derek Hageman <hageman@inthat.cloud>
2019-03-02 10:29:07 +08:00
source "drivers/interrupt_controller/Kconfig.sam0"
drivers: interrupt_controller: Refactor GIC configurations The current GIC configuration scheme is designed to support only one specific type and version of GIC (i.e. GIC-400 that implements the GICv2 interface). This commit adds a set of GIC version configuration symbols that can be selected by the SoC configuration to specify which version of GIC interface is implemented in the SoC. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-12-19 11:41:44 +08:00
source "drivers/interrupt_controller/Kconfig.gic"
driver: intc: add MIWU driver support in NPCX series. The device Multi-Input Wake-Up Unit (MIWU) supports the embedded controller (EC) to exit 'Sleep' or 'Deep Sleep' power state which allows chip has better power consumption. Also, it provides signal conditioning such as 'Level' and 'Edge' trigger type and grouping of external interrupt sources of NVIC. The NPCX series has three identical MIWU modules: MIWU0, MIWU1, MIWU2. Together, they support a total of over 140 internal and/or external wake-up sources. In this CL, we use device tree files to present the relationship bewteen MIWU and the other devices in different npcx series. For npcx7 series, it include: 1. npcx7-miwus-int-map.dtsi: it presents relationship between MIWU group and NVIC interrupt in npcx7. Please notice it isn't 1-to-1 mapping. 2. npcx7-miwus-wui-map.dtsi: it presents relationship between input of MIWU and its source device such as gpio, timer, eSPI VWs and so on. This CL also includes: 1. Add MIWU device tree declarations. 2. MIWU api function declarations and implementation to configure signal conditions and callback function mechanism. They can be be classified into two types. One is for GPIO which connects original gpio callback implemetation and the other is for generic devices such as timer, eSPI, and so on. Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-08-13 18:15:25 +08:00
source "drivers/interrupt_controller/Kconfig.npcx"
drivers/interrupt_controller: Add Intel VT-D interrupt remapping driver Such interrupt remapping controller may be found along with Intel VT-D hardware. Its base-address is via ACPI, and it enables up to 64K interrupt indexes. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-10-13 21:22:27 +08:00
source "drivers/interrupt_controller/Kconfig.intel_vtd"
esp32: drivers: interrupt_controller: add interrupt allocation support Add interrupt allocation support for ESP32. Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-04-13 03:13:54 +08:00
source "drivers/interrupt_controller/Kconfig.esp32"
interrupt_controller: intc_esp32c3: added intc driver For esp32c3 and replaces the hardcoded interrupt attaching procedures with this new driver. Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-08-30 21:04:34 +08:00
source "drivers/interrupt_controller/Kconfig.esp32c3"
Microchip: MEC172x Add aggregated interrupt driver Add driver implementation and header files for a MEC172x aggregated interrupt driver. Enable the parent(ECIA) node to have the driver initialize interrupt hardware for use. Enable child nodes for those GIRQs used for aggregation. Refer to chip documention for the list of GIRQs restricted to aggregation and those which support direct mode. Add chip level device tree node for MEC172x EC interrupt aggregator parent and GIRQ children. Each child node contains a list of sources representing the source bit position in the GIRQ registers. Add DT bindings for ECIA and GIRQ nodes. Add build file(s) and configuration items for the MEC172x ECIA aggregated interrupt driver. Add and enable the MEC172x interrupt driver on the MEC172x evaluation board(EVB). Enable parent node to initialize ECIA hardware. Child nodes are left disabled until a future driver needs them. Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-07-22 02:12:52 +08:00
source "drivers/interrupt_controller/Kconfig.xec"
Kconfig: Introduce RISCV_HAS_CLIC Introduce a new RISCV_HAS_CLIC symbol for platforms using CLIC, reorganize the Kconfigs and make the Nuclei ECLIC depending on the new symbol. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-07 22:27:17 +08:00
source "drivers/interrupt_controller/Kconfig.clic"
drivers: interrupt-controller: add Nuclei ECLIC driver Add support for the ECLIC interrupt controller which is used with the Nuclei processor core. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-11-15 07:34:11 +08:00
drivers: interrupt_controller: initial support for GD32 EXTI Add initial support for the GigaDevice External Interrupt Controller. This driver is required to manage GPIO interrupts. Only EXTI lines 0 to 15 are supported for now (no LVD, RTC, etc.). Driver can be extended in the future to add support for extra EXTI lines. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-12-08 01:59:00 +08:00
source "drivers/interrupt_controller/Kconfig.gd32_exti"
Kconfig: Introduce RISCV_HAS_CLIC Introduce a new RISCV_HAS_CLIC symbol for platforms using CLIC, reorganize the Kconfigs and make the Nuclei ECLIC depending on the new symbol. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-07 22:27:17 +08:00
source "drivers/interrupt_controller/Kconfig.plic"
drivers: interrupt_controller: initial support for NXP S32Z27 EIRQ Add initial support for the NXP S32Z27 SIUL2 External Interrupt Controller. Each SIUL2 node has a child node will act as an interrupt-controller that processes external interrupt signals. This driver is required to manage GPIO interrupts. Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
2022-10-12 15:37:52 +08:00
source "drivers/interrupt_controller/Kconfig.nxp_s32"
x86/bsp: move PIC (i8259) driver to drivers/interrupt_controller Change-Id: I383424667f291ad4985781a7e6566c01c76ba5e0 Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-15 21:20:24 +08:00
endmenu