zephyr/arch/riscv32/Makefile

-include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile

# Put functions and data in their own binary sections so that ld can
# garbage collect them
arch_cflags += $(call cc-option,-ffunction-sections) \
	       $(call cc-option,-fdata-sections)

KBUILD_AFLAGS += $(arch_cflags)
KBUILD_CFLAGS += $(arch_cflags)
KBUILD_CXXFLAGS += $(arch_cflags)

soc-cxxflags ?= $(soc-cflags)
soc-aflags ?= $(soc-cflags)
KBUILD_CFLAGS += $(soc-cflags)
KBUILD_CXXFLAGS += $(soc-cxxflags)
KBUILD_AFLAGS += $(soc-aflags)
arch: added support for the riscv32 architecture RISC-V is an open-source instruction set architecture. Added support for the 32bit version of RISC-V to Zephyr. 1) exceptions/interrupts/faults are handled at the architecture level via the __irq_wrapper handler. Context saving/restoring of registers can be handled at both architecture and SOC levels. If SOC-specific registers need to be saved, SOC level needs to provide __soc_save_context and __soc_restore_context functions that shall be accounted by the architecture level, when corresponding config variable RISCV_SOC_CONTEXT_SAVE is set. 2) As RISC-V architecture does not provide a clear ISA specification about interrupt handling, each RISC-V SOC handles it in its own way. Hence, at the architecture level, the __irq_wrapper handler expects the following functions to be provided by the SOC level: __soc_is_irq: to check if the exception is the result of an interrupt or not. __soc_handle_irq: handle pending IRQ at SOC level (ex: clear pending IRQ in SOC-specific IRQ register) 3) Thread/task scheduling, as well as IRQ offloading are handled via the RISC-V system call ("ecall"), which is also handled via the __irq_wrapper handler. The _Swap asm function just calls "ecall" to generate an exception. 4) As there is no conventional way of handling CPU power save in RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle functions just unlock interrupts and return to the caller, without issuing any CPU power saving instruction. Nonetheless, to allow SOC-level to implement proper CPU power save, nano_cpu_idle and nano_cpu_atomic_idle functions are defined as __weak at the architecture level. Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com> 2017-01-11 07:24:30 +08:00			`-include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile`

			`# Put functions and data in their own binary sections so that ld can`
			`# garbage collect them`
			`arch_cflags += $(call cc-option,-ffunction-sections) \`
			`$(call cc-option,-fdata-sections)`

			`KBUILD_AFLAGS += $(arch_cflags)`
			`KBUILD_CFLAGS += $(arch_cflags)`
			`KBUILD_CXXFLAGS += $(arch_cflags)`

			`soc-cxxflags ?= $(soc-cflags)`
			`soc-aflags ?= $(soc-cflags)`
			`KBUILD_CFLAGS += $(soc-cflags)`
			`KBUILD_CXXFLAGS += $(soc-cxxflags)`
			`KBUILD_AFLAGS += $(soc-aflags)`