2019-11-01 20:45:29 +08:00
|
|
|
# Generic PC platform configuration options
|
2015-05-21 00:40:39 +08:00
|
|
|
|
|
|
|
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
2017-01-19 09:01:01 +08:00
|
|
|
# SPDX-License-Identifier: Apache-2.0
|
2015-05-21 00:40:39 +08:00
|
|
|
|
2015-12-17 21:54:35 +08:00
|
|
|
if SOC_IA32
|
2015-09-25 22:03:08 +08:00
|
|
|
|
2015-12-17 21:54:35 +08:00
|
|
|
config SOC
|
2018-05-26 03:19:21 +08:00
|
|
|
default "ia32"
|
2015-03-13 06:15:28 +08:00
|
|
|
|
|
|
|
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
2015-07-23 04:22:25 +08:00
|
|
|
default 150000000 if LOAPIC_TIMER
|
|
|
|
default 25000000 if HPET_TIMER
|
2015-09-25 22:03:08 +08:00
|
|
|
|
2016-03-01 00:12:40 +08:00
|
|
|
config CLFLUSH_DETECT
|
2018-11-14 00:15:49 +08:00
|
|
|
default y if CACHE_FLUSHING
|
2016-03-01 00:12:40 +08:00
|
|
|
|
2015-12-02 00:42:19 +08:00
|
|
|
if UART_NS16550
|
|
|
|
|
|
|
|
config UART_NS16550_PORT_0
|
2018-11-14 00:15:49 +08:00
|
|
|
default y
|
2015-12-02 00:42:19 +08:00
|
|
|
|
|
|
|
if UART_NS16550_PORT_0
|
|
|
|
|
|
|
|
config UART_NS16550_PORT_0_OPTIONS
|
|
|
|
default 0
|
|
|
|
|
|
|
|
endif # UART_NS16550_PORT_0
|
|
|
|
|
|
|
|
config UART_NS16550_PORT_1
|
2018-11-14 00:15:49 +08:00
|
|
|
default y
|
2015-12-02 00:42:19 +08:00
|
|
|
|
|
|
|
if UART_NS16550_PORT_1
|
|
|
|
|
|
|
|
config UART_NS16550_PORT_1_OPTIONS
|
|
|
|
default 0
|
|
|
|
|
|
|
|
endif # UART_NS16550_PORT_1
|
|
|
|
|
|
|
|
endif # UART_NS16550
|
|
|
|
|
2015-09-25 22:03:08 +08:00
|
|
|
endif
|