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zephyr/soc/riscv/openisa_rv32m1/CMakeLists.txt

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soc: riscv32: add RV32M1 SoC as openisa_rv32m1 The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V 32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC enablement for the RISC-V cores: - basic dtsi, to be extended as additional drivers are added - SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY - system timer driver for RI5CY, based on LPTMR0 peripheral The timer driver will be generalized a bit soon once proper multi-level interrupt support is available. Emphasis is on supporting the RI5CY core as the more capable of the two; the ZERO-RISCY SoC definitions are a good starting point, but additional work setting up a dtsi and initial drivers is needed to support that core. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Michael Scott <mike@foundries.io>
2018-11-25 17:40:57 +08:00
# Copyright (c) 2018 Foundries.io Ltd
#
# SPDX-License-Identifier: Apache-2.0
if(CONFIG_SOC_OPENISA_RV32M1_RI5CY)
if (CONFIG_RISCV_GENERIC_TOOLCHAIN)
zephyr_compile_options(-march=rv32imc)
else()
zephyr_compile_options(-march=rv32imcxpulpv2)
endif()
elseif(CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY)
zephyr_compile_options(-march=rv32imc)
endif()
zephyr_sources(
vector.S
soc_irq.S
wdog.S
soc.c
)
riscv: linker.ld: Port vector table to zephyr_linker_sources() Put it in its own linker file snippet. Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2019-11-29 20:31:53 +08:00
zephyr_linker_sources(TEXT_START SORT_KEY 0x0vectors vector_table.ld)