2021-10-19 04:44:45 +08:00
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# Copyright (c) 2021 Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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description: Microchip XEC eSPI Virtual Wire routing
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compatible: "microchip,xec-espi-vw-routing"
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2022-12-13 06:56:06 +08:00
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include: [base.yaml]
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2021-10-19 04:44:45 +08:00
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child-binding:
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2023-02-16 18:28:54 +08:00
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description: |
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Child node containing the routing of an eSPI virtual wire to the SoC
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VW registers and ECIA GIRQ registers.
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properties:
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vw-reg:
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type: array
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required: true
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description: vw signal's register index and vw bitmask.
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vw-girq:
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type: array
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description: |
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Routing of MSVW source to aggregated GIRQs
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For example, OOB_RST_WARN is source 2 of MSVW01 routed
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to GIRQ24 b[5]. vw-girq = <24 5>;
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reset-state:
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type: string
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description: |
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Optional default virtual wire state on reset (0 or 1).
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If the property is not present hardware default is used.
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enum:
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- "HW_DFLT"
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- "0"
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- "1"
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reset-source:
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type: string
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description: |
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Optional reset source in addition to chip reset.
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0 is ESPI_RESET, 1 is RESET_SYS, 2 is RESET_SIO,
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and 3 is ESPI Platform Reset. If this property is not
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present the hardware default is used. Note: reset source
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affects all four virtual wires in the VW group.
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enum:
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- "HW_DFLT"
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- "ESPI_RESET"
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- "RESET_SYS"
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- "RESET_SIO"
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- "PLTRST"
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