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zephyr/boards/xtensa/xt-sim/xt-sim_D_233L_defconfig

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sanitycheck: build more Xtensa SOCs Now that we can specify what toolchain is intended for each SOC, enable some more SOCs to be built. A full sanitycheck run will require the installation of both RF-2016.4 and RG-2016.4 releases. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-18 01:36:40 +08:00
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_IPM_CONSOLE_STACK_SIZE=2048
CONFIG_XTENSA=y
CONFIG_SOC_D_233L=y
CONFIG_BOARD_XT_SIM=y
CONFIG_CONSOLE=y
arch: xtensa: Convert Xtensa port to use gen_isr_table The Xtensa port was the only one remaining to be converted to the new way of connecting interrupts in Zephyr. Some things are still unconverted, mainly the exception table, and this will be performed another time. Of note: _irq_priority_set() isn't called on _ARCH_IRQ_CONNECT(), since IRQs can't change priority on Xtensa: while the architecture has the concept of interrupt priority levels, each line has a fixed level and can't be changed. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-07-08 01:35:18 +08:00
CONFIG_SW_ISR_TABLE=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
boards: xt-sim: make board depend on SIMULATOR_XTENSA Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-12 00:25:39 +08:00
CONFIG_SIMULATOR_XTENSA=y