2021-02-16 03:40:38 +08:00
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/*
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* Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT espressif_esp32_timer
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/* Include esp-idf headers first to avoid redefining BIT() macro */
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#include <soc/rtc_cntl_reg.h>
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#include <soc/timer_group_reg.h>
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2024-03-05 22:19:27 +08:00
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#include <periph_ctrl.h>
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#include <driver/timer_types_legacy.h>
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2021-02-16 03:40:38 +08:00
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#include <soc/periph_defs.h>
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#include <hal/timer_hal.h>
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2024-03-05 22:19:27 +08:00
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#include <hal/timer_ll.h>
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2021-02-16 03:40:38 +08:00
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#include <string.h>
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2022-05-06 16:25:46 +08:00
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#include <zephyr/drivers/counter.h>
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2022-10-12 20:25:33 +08:00
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#include <zephyr/spinlock.h>
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#include <zephyr/kernel.h>
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2024-08-06 01:23:37 +08:00
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#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
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2022-05-06 16:25:46 +08:00
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#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
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2024-08-06 01:23:37 +08:00
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#else
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#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
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2021-11-02 08:25:57 +08:00
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#endif
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2022-05-06 16:25:46 +08:00
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#include <zephyr/device.h>
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#include <zephyr/logging/log.h>
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2021-02-16 03:40:38 +08:00
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LOG_MODULE_REGISTER(esp32_counter, CONFIG_COUNTER_LOG_LEVEL);
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2024-08-06 01:23:37 +08:00
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#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
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2021-11-02 08:25:57 +08:00
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#define ISR_HANDLER isr_handler_t
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#else
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#define ISR_HANDLER intr_handler_t
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#endif
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2021-04-17 05:15:11 +08:00
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static void counter_esp32_isr(void *arg);
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typedef bool (*timer_isr_t)(void *);
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2021-02-16 03:40:38 +08:00
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struct timer_isr_func_t {
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timer_isr_t fn;
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void *args;
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2021-04-17 05:15:11 +08:00
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struct intr_handle_data_t *timer_isr_handle;
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2021-02-16 03:40:38 +08:00
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timer_group_t isr_timer_group;
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};
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struct counter_esp32_config {
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struct counter_config_info counter_info;
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timer_config_t config;
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timer_group_t group;
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2022-07-07 05:21:28 +08:00
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timer_idx_t index;
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2021-04-17 05:15:11 +08:00
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int irq_source;
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2024-08-20 02:21:16 +08:00
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int irq_priority;
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2024-08-20 02:23:22 +08:00
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int irq_flags;
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2021-02-16 03:40:38 +08:00
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};
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struct counter_esp32_data {
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struct counter_alarm_cfg alarm_cfg;
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uint32_t ticks;
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2022-07-07 05:21:28 +08:00
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timer_hal_context_t hal_ctx;
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struct timer_isr_func_t timer_isr_fun;
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2021-02-16 03:40:38 +08:00
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};
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static struct k_spinlock lock;
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static int counter_esp32_init(const struct device *dev)
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{
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2022-01-18 21:01:39 +08:00
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const struct counter_esp32_config *cfg = dev->config;
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struct counter_esp32_data *data = dev->data;
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2021-02-16 03:40:38 +08:00
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2022-07-07 05:21:28 +08:00
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switch (cfg->group) {
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case TIMER_GROUP_0:
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2021-02-16 03:40:38 +08:00
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periph_module_enable(PERIPH_TIMG0_MODULE);
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2022-07-07 05:21:28 +08:00
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break;
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2024-08-06 01:23:37 +08:00
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#if !defined(CONFIG_SOC_SERIES_ESP32C2)
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2022-07-07 05:21:28 +08:00
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case TIMER_GROUP_1:
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2021-02-16 03:40:38 +08:00
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periph_module_enable(PERIPH_TIMG1_MODULE);
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2022-07-07 05:21:28 +08:00
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break;
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2024-08-06 01:23:37 +08:00
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#endif
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2022-07-07 05:21:28 +08:00
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default:
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2021-02-16 03:40:38 +08:00
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return -ENOTSUP;
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}
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k_spinlock_key_t key = k_spin_lock(&lock);
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2022-07-07 05:21:28 +08:00
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timer_hal_init(&data->hal_ctx, cfg->group, cfg->index);
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2022-01-18 21:01:39 +08:00
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data->alarm_cfg.callback = NULL;
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2024-03-05 22:19:27 +08:00
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timer_ll_enable_intr(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id),
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false);
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timer_ll_clear_intr_status(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id));
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timer_ll_enable_auto_reload(data->hal_ctx.dev, data->hal_ctx.timer_id,
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cfg->config.auto_reload);
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timer_ll_set_clock_prescale(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.divider);
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timer_ll_set_count_direction(data->hal_ctx.dev, data->hal_ctx.timer_id,
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cfg->config.counter_dir);
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timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.alarm_en);
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timer_ll_set_reload_value(data->hal_ctx.dev, data->hal_ctx.timer_id, 0);
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timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.counter_en);
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2024-08-20 02:21:16 +08:00
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2021-02-16 03:40:38 +08:00
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k_spin_unlock(&lock, key);
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2024-06-28 20:08:33 +08:00
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int ret = esp_intr_alloc(cfg->irq_source,
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2024-08-20 02:23:22 +08:00
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ESP_PRIO_TO_FLAGS(cfg->irq_priority) |
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ESP_INT_FLAGS_CHECK(cfg->irq_flags),
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2024-06-28 20:08:33 +08:00
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(ISR_HANDLER)counter_esp32_isr, (void *)dev, NULL);
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if (ret != 0) {
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LOG_ERR("could not allocate interrupt (err %d)", ret);
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}
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return ret;
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2021-02-16 03:40:38 +08:00
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}
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static int counter_esp32_start(const struct device *dev)
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{
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2022-07-07 05:21:28 +08:00
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struct counter_esp32_data *data = dev->data;
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2021-02-16 03:40:38 +08:00
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k_spinlock_key_t key = k_spin_lock(&lock);
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2024-03-05 22:19:27 +08:00
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timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_START);
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2021-02-16 03:40:38 +08:00
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k_spin_unlock(&lock, key);
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return 0;
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}
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static int counter_esp32_stop(const struct device *dev)
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{
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2022-07-07 05:21:28 +08:00
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struct counter_esp32_data *data = dev->data;
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2021-02-16 03:40:38 +08:00
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k_spinlock_key_t key = k_spin_lock(&lock);
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2024-03-05 22:19:27 +08:00
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timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_PAUSE);
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2021-02-16 03:40:38 +08:00
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k_spin_unlock(&lock, key);
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return 0;
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}
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static int counter_esp32_get_value(const struct device *dev, uint32_t *ticks)
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{
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2022-07-07 05:21:28 +08:00
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struct counter_esp32_data *data = dev->data;
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2021-02-16 03:40:38 +08:00
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k_spinlock_key_t key = k_spin_lock(&lock);
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2024-10-10 08:25:11 +08:00
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timer_ll_trigger_soft_capture(data->hal_ctx.dev, data->hal_ctx.timer_id);
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*ticks = (uint32_t)timer_ll_get_counter_value(data->hal_ctx.dev, data->hal_ctx.timer_id);
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k_spin_unlock(&lock, key);
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return 0;
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}
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static int counter_esp32_get_value_64(const struct device *dev, uint64_t *ticks)
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{
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struct counter_esp32_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&lock);
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timer_ll_trigger_soft_capture(data->hal_ctx.dev, data->hal_ctx.timer_id);
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2024-03-05 22:19:27 +08:00
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*ticks = timer_ll_get_counter_value(data->hal_ctx.dev, data->hal_ctx.timer_id);
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2024-10-10 08:25:11 +08:00
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2021-02-16 03:40:38 +08:00
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k_spin_unlock(&lock, key);
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return 0;
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}
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static int counter_esp32_set_alarm(const struct device *dev, uint8_t chan_id,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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ARG_UNUSED(chan_id);
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2022-01-20 22:04:35 +08:00
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struct counter_esp32_data *data = dev->data;
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2021-02-16 03:40:38 +08:00
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uint32_t now;
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counter_esp32_get_value(dev, &now);
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2022-09-14 21:28:38 +08:00
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2021-02-16 03:40:38 +08:00
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k_spinlock_key_t key = k_spin_lock(&lock);
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2022-09-14 21:28:38 +08:00
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if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
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2024-03-05 22:19:27 +08:00
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timer_ll_set_alarm_value(data->hal_ctx.dev, data->hal_ctx.timer_id,
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(now + alarm_cfg->ticks));
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2022-09-14 21:28:38 +08:00
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} else {
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2024-03-05 22:19:27 +08:00
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timer_ll_set_alarm_value(data->hal_ctx.dev, data->hal_ctx.timer_id,
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alarm_cfg->ticks);
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2022-09-14 21:28:38 +08:00
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}
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2024-03-05 22:19:27 +08:00
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timer_ll_enable_intr(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id), true);
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timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_ALARM_EN);
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2022-01-18 21:01:39 +08:00
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data->alarm_cfg.callback = alarm_cfg->callback;
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data->alarm_cfg.user_data = alarm_cfg->user_data;
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2021-02-16 03:40:38 +08:00
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k_spin_unlock(&lock, key);
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return 0;
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}
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static int counter_esp32_cancel_alarm(const struct device *dev, uint8_t chan_id)
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{
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ARG_UNUSED(chan_id);
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2022-07-07 05:21:28 +08:00
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struct counter_esp32_data *data = dev->data;
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2021-02-16 03:40:38 +08:00
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k_spinlock_key_t key = k_spin_lock(&lock);
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2024-03-05 22:19:27 +08:00
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timer_ll_enable_intr(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id),
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false);
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timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_ALARM_DIS);
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2021-02-16 03:40:38 +08:00
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k_spin_unlock(&lock, key);
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return 0;
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}
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static int counter_esp32_set_top_value(const struct device *dev,
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const struct counter_top_cfg *cfg)
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{
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2022-01-18 21:01:39 +08:00
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const struct counter_esp32_config *config = dev->config;
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if (cfg->ticks != config->counter_info.max_top_value) {
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2021-02-16 03:40:38 +08:00
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return -ENOTSUP;
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} else {
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return 0;
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}
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}
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static uint32_t counter_esp32_get_pending_int(const struct device *dev)
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{
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2022-07-07 05:21:28 +08:00
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struct counter_esp32_data *data = dev->data;
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2024-03-05 22:19:27 +08:00
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return timer_ll_get_intr_status(data->hal_ctx.dev);
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2021-02-16 03:40:38 +08:00
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}
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static uint32_t counter_esp32_get_top_value(const struct device *dev)
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{
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2022-01-18 21:01:39 +08:00
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const struct counter_esp32_config *config = dev->config;
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return config->counter_info.max_top_value;
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2021-02-16 03:40:38 +08:00
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}
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static const struct counter_driver_api counter_api = {
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.start = counter_esp32_start,
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.stop = counter_esp32_stop,
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.get_value = counter_esp32_get_value,
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2024-10-10 08:25:11 +08:00
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.get_value_64 = counter_esp32_get_value_64,
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2021-02-16 03:40:38 +08:00
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.set_alarm = counter_esp32_set_alarm,
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.cancel_alarm = counter_esp32_cancel_alarm,
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.set_top_value = counter_esp32_set_top_value,
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.get_pending_int = counter_esp32_get_pending_int,
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.get_top_value = counter_esp32_get_top_value,
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};
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2021-04-17 05:15:11 +08:00
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static void counter_esp32_isr(void *arg)
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2021-02-16 03:40:38 +08:00
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{
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2022-01-06 21:10:19 +08:00
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const struct device *dev = (const struct device *)arg;
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2022-01-18 21:01:39 +08:00
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struct counter_esp32_data *data = dev->data;
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2021-02-16 03:40:38 +08:00
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uint32_t now;
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2022-07-07 05:21:28 +08:00
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counter_esp32_cancel_alarm(dev, 0);
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2021-02-16 03:40:38 +08:00
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counter_esp32_get_value(dev, &now);
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2022-07-07 05:21:28 +08:00
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if (data->alarm_cfg.callback) {
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data->alarm_cfg.callback(dev, 0, now, data->alarm_cfg.user_data);
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2021-02-16 03:40:38 +08:00
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}
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2024-03-05 22:19:27 +08:00
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timer_ll_clear_intr_status(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id));
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2021-02-16 03:40:38 +08:00
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}
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2022-07-07 05:21:28 +08:00
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#define ESP32_COUNTER_GET_CLK_DIV(idx) \
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(((DT_INST_PROP(idx, prescaler) & UINT16_MAX) < 2) ? \
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2 : (DT_INST_PROP(idx, prescaler) & UINT16_MAX))
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#define ESP32_COUNTER_INIT(idx) \
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2021-02-16 03:40:38 +08:00
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\
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2022-07-07 05:21:28 +08:00
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static struct counter_esp32_data counter_data_##idx; \
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2021-02-16 03:40:38 +08:00
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\
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2022-07-07 05:21:28 +08:00
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static const struct counter_esp32_config counter_config_##idx = { \
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2021-02-16 03:40:38 +08:00
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.counter_info = { \
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.max_top_value = UINT32_MAX, \
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2022-07-07 05:21:28 +08:00
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.freq = (APB_CLK_FREQ / ESP32_COUNTER_GET_CLK_DIV(idx)), \
|
2021-02-16 03:40:38 +08:00
|
|
|
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
|
|
|
|
.channels = 1 \
|
|
|
|
}, \
|
|
|
|
.config = { \
|
|
|
|
.alarm_en = TIMER_ALARM_DIS, \
|
|
|
|
.counter_en = TIMER_START, \
|
|
|
|
.intr_type = TIMER_INTR_LEVEL, \
|
|
|
|
.counter_dir = TIMER_COUNT_UP, \
|
|
|
|
.auto_reload = TIMER_AUTORELOAD_DIS, \
|
2022-07-07 05:21:28 +08:00
|
|
|
.divider = ESP32_COUNTER_GET_CLK_DIV(idx), \
|
2021-02-16 03:40:38 +08:00
|
|
|
}, \
|
2022-07-07 05:21:28 +08:00
|
|
|
.group = DT_INST_PROP(idx, group), \
|
|
|
|
.index = DT_INST_PROP(idx, index), \
|
2024-08-20 02:21:16 +08:00
|
|
|
.irq_source = DT_INST_IRQ_BY_IDX(idx, 0, irq), \
|
2024-08-20 02:23:22 +08:00
|
|
|
.irq_priority = DT_INST_IRQ_BY_IDX(idx, 0, priority), \
|
|
|
|
.irq_flags = DT_INST_IRQ_BY_IDX(idx, 0, flags) \
|
2021-02-16 03:40:38 +08:00
|
|
|
}; \
|
|
|
|
\
|
|
|
|
\
|
2022-07-07 05:21:28 +08:00
|
|
|
DEVICE_DT_INST_DEFINE(idx, \
|
2021-02-16 03:40:38 +08:00
|
|
|
counter_esp32_init, \
|
2022-07-07 05:21:28 +08:00
|
|
|
NULL, \
|
|
|
|
&counter_data_##idx, \
|
|
|
|
&counter_config_##idx, \
|
|
|
|
PRE_KERNEL_1, \
|
|
|
|
CONFIG_COUNTER_INIT_PRIORITY, \
|
|
|
|
&counter_api);
|
2021-02-16 03:40:38 +08:00
|
|
|
|
2021-11-02 08:25:57 +08:00
|
|
|
DT_INST_FOREACH_STATUS_OKAY(ESP32_COUNTER_INIT);
|