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zephyr/include/linker/linker-tool-gcc.h

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First commit Signed-off-by: <inaky.perez-gonzalez@intel.com>
2015-04-11 07:44:37 +08:00
/*
* Copyright (c) 2013-2014, Wind River Systems, Inc.
*
license: Replace Apache boilerplate with SPDX tag Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 09:01:01 +08:00
* SPDX-License-Identifier: Apache-2.0
First commit Signed-off-by: <inaky.perez-gonzalez@intel.com>
2015-04-11 07:44:37 +08:00
*/
Fixed file description and applied doxygen style Removed old style file description and documnetation and apply doxygen synatx. Change-Id: I3ac9f06d4f574bf3c79c6f6044cec3a7e2f6e4c8 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-12-04 23:09:39 +08:00
/**
* @file
* @brief GCC toolchain linker defs
*
checkpatch: warning - block_comment_style Change-Id: I6da43e41f9c6efee577b70513ec368ae3cce0144 Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-10-21 00:42:33 +08:00
* This header file defines the necessary macros used by the linker script for
* use with the GCC linker.
doxygen: change comment style to match javadoc The change replaces multiple asterisks to ** at the beginning of comments and adds a space before the asterisks at the beginning of lines. Change-Id: I7656bde3bf4d9a31e38941e43b580520432dabc1 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-07-02 05:22:39 +08:00
*/
First commit Signed-off-by: <inaky.perez-gonzalez@intel.com>
2015-04-11 07:44:37 +08:00
#ifndef __LINKER_TOOL_GCC_H
#define __LINKER_TOOL_GCC_H
linker-tool-gcc: improve readability This no longer defaults to X86 and instead throws an error if a supported arch isn't found. Output format now checks CONFIG_ARM instead of Cortex M3, should be the same for all ARM chips. Change-Id: Ib9bf07ad93a44b3f7cdac7b52432110776eb23fd Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-04-27 01:22:39 +08:00
#if defined(CONFIG_ARM)
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
First commit Signed-off-by: <inaky.perez-gonzalez@intel.com>
2015-04-11 07:44:37 +08:00
#elif defined(CONFIG_ARC)
linker-tool-gcc: improve readability This no longer defaults to X86 and instead throws an error if a supported arch isn't found. Output format now checks CONFIG_ARM instead of Cortex M3, should be the same for all ARM chips. Change-Id: Ib9bf07ad93a44b3f7cdac7b52432110776eb23fd Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-04-27 01:22:39 +08:00
OUTPUT_FORMAT("elf32-littlearc", "elf32-bigarc", "elf32-littlearc")
#elif defined(CONFIG_X86)
#if defined(__IAMCU)
OUTPUT_FORMAT("elf32-iamcu")
OUTPUT_ARCH(iamcu:intel)
#else
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
OUTPUT_ARCH(i386)
#endif
nios2: basic build, non-functional Basic build framework for Nios2. Everything is stubbed out, we just want to have a build going so that we can start to parallelize implementation tasks. This patch is not intended to be functional, but should be able to produce a binary for all the nanokernel-based sanity checks. Change-Id: I12dd8ca4a2273f7662bee46175822c9bbd99202a Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-04-22 05:47:09 +08:00
#elif defined(CONFIG_NIOS2)
OUTPUT_FORMAT("elf32-littlenios2", "elf32-bignios2", "elf32-littlenios2")
arch: added support for the riscv32 architecture RISC-V is an open-source instruction set architecture. Added support for the 32bit version of RISC-V to Zephyr. 1) exceptions/interrupts/faults are handled at the architecture level via the __irq_wrapper handler. Context saving/restoring of registers can be handled at both architecture and SOC levels. If SOC-specific registers need to be saved, SOC level needs to provide __soc_save_context and __soc_restore_context functions that shall be accounted by the architecture level, when corresponding config variable RISCV_SOC_CONTEXT_SAVE is set. 2) As RISC-V architecture does not provide a clear ISA specification about interrupt handling, each RISC-V SOC handles it in its own way. Hence, at the architecture level, the __irq_wrapper handler expects the following functions to be provided by the SOC level: __soc_is_irq: to check if the exception is the result of an interrupt or not. __soc_handle_irq: handle pending IRQ at SOC level (ex: clear pending IRQ in SOC-specific IRQ register) 3) Thread/task scheduling, as well as IRQ offloading are handled via the RISC-V system call ("ecall"), which is also handled via the __irq_wrapper handler. The _Swap asm function just calls "ecall" to generate an exception. 4) As there is no conventional way of handling CPU power save in RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle functions just unlock interrupts and return to the caller, without issuing any CPU power saving instruction. Nonetheless, to allow SOC-level to implement proper CPU power save, nano_cpu_idle and nano_cpu_atomic_idle functions are defined as __weak at the architecture level. Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 07:24:30 +08:00
#elif defined(CONFIG_RISCV32)
OUTPUT_ARCH(riscv)
OUTPUT_FORMAT("elf32-littleriscv")
Xtensa port: Added linker script for several Xtensa cores. Change-Id: I7a40d5f0c3fe8d25623b88f06523cb62e4ba4706 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:25:40 +08:00
#elif defined(CONFIG_XTENSA)
/* Not needed */
First commit Signed-off-by: <inaky.perez-gonzalez@intel.com>
2015-04-11 07:44:37 +08:00
#else
linker-tool-gcc: improve readability This no longer defaults to X86 and instead throws an error if a supported arch isn't found. Output format now checks CONFIG_ARM instead of Cortex M3, should be the same for all ARM chips. Change-Id: Ib9bf07ad93a44b3f7cdac7b52432110776eb23fd Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-04-27 01:22:39 +08:00
#error Arch not supported.
toolchain: add support for iamcu toolchain See https://groups.google.com/forum/#!topic/ia32-abi/cn7TM6J_TIg for more details. • Support IA32 without FPU. • Minimum ISA: Pentium ISA without x87 FPU instructions. • Don't allow mixing i386 object files with Intel MCU object files. • Support floating point with software emulation: a. Long double is the same as double. b. Use __float80 for 80-bit double. • Minimize memory footprint: a. Code size b. Data size c. Stack size Here is the draft of Intel MCU psABI. The differences from IA32 psABI are 1. The minimum instruction set is Intel Pentium ISA minus instructions for x87 floating point unit. 2. There are no x87 floating point registers. 3. There are no vector registers. 4. Segment registers are optional. 5. Support for TLS relocations are optional. 6. Scalar types larger than 4 bytes are aligned to 4 bytes. 7. There are no vector types. 8. _Decimal32, _Decimal64, and _Decimal128 types are optional. 9. long double type is the same as double. 10. float, double and long double types are passed and returned in general purpose registers. 11. _Decimal32 and _Decimal64 types are passed in general purpose registers. 12. Aggregate types no larger than 8 bytes are passed and returned in general purpose registers. 13. Stack is 4-byte aligned. 14. The auxiliary vector support is optional. 15. Register %edx has undefined value at process entry. 16. New ELF machine code: EM_IAMCU. 17. New predefined C/C++ pre-processor symbols: __iamcu and __iamcu__ Change-Id: I6a0c45ad22d8f710b6f37a041aaa2fc1bf0b1c39 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-06-20 11:37:23 +08:00
#endif
First commit Signed-off-by: <inaky.perez-gonzalez@intel.com>
2015-04-11 07:44:37 +08:00
/*
* The GROUP_START() and GROUP_END() macros are used to define a group
* of sections located in one memory area, such as RAM, ROM, etc.
* The <where> parameter is the name of the memory area.
*/
#define GROUP_START(where)
#define GROUP_END(where)
/*
* The GROUP_LINK_IN() macro is located at the end of the section
* description and tells the linker that this section is located in
* the memory area specified by <where> argument.
*/
#define GROUP_LINK_IN(where) > where
x86 link: Specify ALIGN_WITH_INPUT for XIP data sections Binutils ld has an annoying misfeature (apparently a regression from a few years ago) that alignment directives (and alignment specifiers on symbols) apply only to the runtime addresses and not, apparently, to the load address region specified with the "AT>" syntax. The net result is that by default the LMA output ends up too small for the addresses generated in RAM. See here for some details: https://sourceware.org/ml/binutils/2013-06/msg00246.html https://sourceware.org/ml/binutils/2014-01/msg00350.html The required workaround/fix is that AFAICT any section which can have inherit a separate VMA vs. LMA from a previous section must specify an "ALIGN_WITH_INPUT" attribute. Otherwise the sections will get out of sync and the XIP data will be wrong at runtime. No, I don't know why this isn't the default behavior. A further complexity is that this feature only works as advertised when the section is declared with the "AT> region" syntax after the block and not "AT(address)" in the header. If you use the header syntax (with or without ALIGN_WITH_INPUT), ld appears to DOUBLE-apply padding and the LMA ends up to big. This is almost certainly a binutils bug, but it's trivial to work around (and the working syntax is actually cleaner) so we adjust the usage here. Note finally that this patch includes an effective reversion of commit d82e9dd9 ("x86: HACK force alignment for _k_task_list section"), which was an earlier workaround for what seems to be the same issue. Jira: ZEP-955 Change-Id: I2accd92901cb61fb546658b87d6752c1cd14de3a Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2016-09-23 05:20:56 +08:00
/*
* As GROUP_LINK_IN(), but takes a second argument indicating the
* memory region (e.g. "ROM") for the load address. Used for
* initialized data sections that on XIP platforms must be copied at
* startup.
*
* And, because output directives in GNU ld are "sticky", this must
* also be used on the first section *after* such an initialized data
* section, specifying the same memory region (e.g. "RAM") for both
* vregion and lregion.
*/
#ifdef CONFIG_XIP
#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion AT> lregion
#else
#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion
#endif
First commit Signed-off-by: <inaky.perez-gonzalez@intel.com>
2015-04-11 07:44:37 +08:00
/*
* The GROUP_FOLLOWS_AT() macro is located at the end of the section
* and indicates that the section does not specify an address at which
* it is to be loaded, but that it follows a section which did specify
* such an address
*/
#define GROUP_FOLLOWS_AT(where) AT > where
/*
* The SECTION_PROLOGUE() macro is used to define the beginning of a section.
* The <name> parameter is the name of the section, and the <option> parameter
* is to include any special options such as (NOLOAD). Page alignment has its
* own parameter since it needs abstraction across the different toolchains.
* If not required, the <options> and <align> parameters should be left blank.
*/
#define SECTION_PROLOGUE(name, options, align) name options : align
/*
x86 link: Specify ALIGN_WITH_INPUT for XIP data sections Binutils ld has an annoying misfeature (apparently a regression from a few years ago) that alignment directives (and alignment specifiers on symbols) apply only to the runtime addresses and not, apparently, to the load address region specified with the "AT>" syntax. The net result is that by default the LMA output ends up too small for the addresses generated in RAM. See here for some details: https://sourceware.org/ml/binutils/2013-06/msg00246.html https://sourceware.org/ml/binutils/2014-01/msg00350.html The required workaround/fix is that AFAICT any section which can have inherit a separate VMA vs. LMA from a previous section must specify an "ALIGN_WITH_INPUT" attribute. Otherwise the sections will get out of sync and the XIP data will be wrong at runtime. No, I don't know why this isn't the default behavior. A further complexity is that this feature only works as advertised when the section is declared with the "AT> region" syntax after the block and not "AT(address)" in the header. If you use the header syntax (with or without ALIGN_WITH_INPUT), ld appears to DOUBLE-apply padding and the LMA ends up to big. This is almost certainly a binutils bug, but it's trivial to work around (and the working syntax is actually cleaner) so we adjust the usage here. Note finally that this patch includes an effective reversion of commit d82e9dd9 ("x86: HACK force alignment for _k_task_list section"), which was an earlier workaround for what seems to be the same issue. Jira: ZEP-955 Change-Id: I2accd92901cb61fb546658b87d6752c1cd14de3a Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2016-09-23 05:20:56 +08:00
* As for SECTION_PROLOGUE(), except that this one must (!) be used
spell: fix comment typos: /include Change-Id: I20d315ef5f8a2da5cfe28b194126907adda9e13c Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-04-19 06:56:26 +08:00
* for data sections which on XIP platforms will have differing
x86 link: Specify ALIGN_WITH_INPUT for XIP data sections Binutils ld has an annoying misfeature (apparently a regression from a few years ago) that alignment directives (and alignment specifiers on symbols) apply only to the runtime addresses and not, apparently, to the load address region specified with the "AT>" syntax. The net result is that by default the LMA output ends up too small for the addresses generated in RAM. See here for some details: https://sourceware.org/ml/binutils/2013-06/msg00246.html https://sourceware.org/ml/binutils/2014-01/msg00350.html The required workaround/fix is that AFAICT any section which can have inherit a separate VMA vs. LMA from a previous section must specify an "ALIGN_WITH_INPUT" attribute. Otherwise the sections will get out of sync and the XIP data will be wrong at runtime. No, I don't know why this isn't the default behavior. A further complexity is that this feature only works as advertised when the section is declared with the "AT> region" syntax after the block and not "AT(address)" in the header. If you use the header syntax (with or without ALIGN_WITH_INPUT), ld appears to DOUBLE-apply padding and the LMA ends up to big. This is almost certainly a binutils bug, but it's trivial to work around (and the working syntax is actually cleaner) so we adjust the usage here. Note finally that this patch includes an effective reversion of commit d82e9dd9 ("x86: HACK force alignment for _k_task_list section"), which was an earlier workaround for what seems to be the same issue. Jira: ZEP-955 Change-Id: I2accd92901cb61fb546658b87d6752c1cd14de3a Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2016-09-23 05:20:56 +08:00
* virtual and load addresses (i.e. they'll be copied into RAM at
* program startup). Such a section must (!) also use
* GROUP_LINK_IN_LMA to specify the correct output load address.
First commit Signed-off-by: <inaky.perez-gonzalez@intel.com>
2015-04-11 07:44:37 +08:00
*/
x86 link: Specify ALIGN_WITH_INPUT for XIP data sections Binutils ld has an annoying misfeature (apparently a regression from a few years ago) that alignment directives (and alignment specifiers on symbols) apply only to the runtime addresses and not, apparently, to the load address region specified with the "AT>" syntax. The net result is that by default the LMA output ends up too small for the addresses generated in RAM. See here for some details: https://sourceware.org/ml/binutils/2013-06/msg00246.html https://sourceware.org/ml/binutils/2014-01/msg00350.html The required workaround/fix is that AFAICT any section which can have inherit a separate VMA vs. LMA from a previous section must specify an "ALIGN_WITH_INPUT" attribute. Otherwise the sections will get out of sync and the XIP data will be wrong at runtime. No, I don't know why this isn't the default behavior. A further complexity is that this feature only works as advertised when the section is declared with the "AT> region" syntax after the block and not "AT(address)" in the header. If you use the header syntax (with or without ALIGN_WITH_INPUT), ld appears to DOUBLE-apply padding and the LMA ends up to big. This is almost certainly a binutils bug, but it's trivial to work around (and the working syntax is actually cleaner) so we adjust the usage here. Note finally that this patch includes an effective reversion of commit d82e9dd9 ("x86: HACK force alignment for _k_task_list section"), which was an earlier workaround for what seems to be the same issue. Jira: ZEP-955 Change-Id: I2accd92901cb61fb546658b87d6752c1cd14de3a Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2016-09-23 05:20:56 +08:00
#ifdef CONFIG_XIP
#define SECTION_DATA_PROLOGUE(name, options, align) \
name options : ALIGN_WITH_INPUT align
#else
#define SECTION_DATA_PROLOGUE(name, options, align) name options : align
#endif
First commit Signed-off-by: <inaky.perez-gonzalez@intel.com>
2015-04-11 07:44:37 +08:00
#define SORT_BY_NAME(x) SORT(x)
#define OPTIONAL
#define COMMON_SYMBOLS *(COMMON)
#endif /* !__LINKER_TOOL_GCC_H */