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zephyr/soc/x86/apollo_lake/soc.h

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arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
/*
gpio: intel_apl: rework driver for pin_mask callback To avoid confusion, callbacks using ordinal pin numbers is going to be reverted. So the driver has to be re-worked to expose multiple devices so each device has 32 pins. Also fixes #12765 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-01-30 11:34:41 +08:00
* Copyright (c) 2018-2019, Intel Corporation
arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
* Copyright (c) 2010-2015, Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Board configuration macros for the Apollo Lake SoC
*
* This header file is used to specify and describe soc-level aspects for
* the 'Apollo Lake' SoC.
*/
#ifndef __SOC_H_
#define __SOC_H_
soc: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all soc code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 17:11:04 +08:00
#include <zephyr/sys/util.h>
arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
#ifndef _ASMLANGUAGE
soc: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all soc code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 17:11:04 +08:00
#include <zephyr/device.h>
random: Rename random header rand32.h does not make much sense, since the random subsystem provides more APIs than just getting a random 32 bits value. Rename it to random.h and get consistently with other subsystems. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-10-07 06:38:53 +08:00
#include <zephyr/random/random.h>
arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
#endif
drivers: gpio: Generic GPIO driver for Intel SoC Modified GPIO driver for Intel APL SoC to have a generic driver for all Intel SoC. Signed-off-by: U Divya <u.divya@intel.com>
2021-05-07 01:21:19 +08:00
#ifdef CONFIG_GPIO_INTEL
gpio: add driver for Intel Apollo Lake SoC This adds a driver for GPIO controller on the Intel Apollo Lake SoC. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-09-20 01:15:12 +08:00
#include "soc_gpio.h"
gpio: intel_apl: rework driver for pin_mask callback To avoid confusion, callbacks using ordinal pin numbers is going to be reverted. So the driver has to be re-worked to expose multiple devices so each device has 32 pins. Also fixes #12765 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-01-30 11:34:41 +08:00
#endif
gpio: add driver for Intel Apollo Lake SoC This adds a driver for GPIO controller on the Intel Apollo Lake SoC. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-09-20 01:15:12 +08:00
soc: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all soc code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 17:11:04 +08:00
#include <zephyr/drivers/pcie/pcie.h>
arch/x86: early_serial cleanup Various cleanups to the x86 early serial driver, mostly with the goal of simplifying its deployment during board bringup (which is really the only reason it exists in the first place): + Configure it =y by default. While there are surely constrained environments that will want to disable it, this is a TINY driver, and it serves a very important role for niche tasks. It should be built always to make sure it works everywhere. + Decouple from devicetree as much as possible. This code HAS to work during board bringup, often with configurations cribbed from other machines, before proper configuration gets written. Experimentally, devicetree errors tend to be easy to make, and without a working console impossible to diagnose. Specify the device via integer constants in soc.h (in the case of IOPORT access, we already had such a symbol) so that the path from what the developer intends to what the code executes is as short and obvious as possible. Unfortunately I'm not allowed to remove devicetree entirely here, but at least a developer adding a new platform will be able to override it in an obvious way instead of banging blindly on the other side of a DTS compiler. + Don't try to probe the PCI device by ID to "verify". While this sounds like a good idea, in practice it's just an extra thing to get wrong. If we bail on our early console because someone (yes, that's me) got the bus/device/function right but typoed the VID/DID numbers, we're doing no one any favors. + Remove the word-sized-I/O feature. This is a x86 driver for a PCI device. No known PC hardware requires that UART register access be done in dword units (in fact doing so would be a violation of the PCI specifciation as I understand it). It looks to have been cut and pasted from the ns16550 driver, remove. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-06-12 22:59:28 +08:00
soc: x86: Used fixed BDF values for early serial Since DTS doesn't contain the BDF anymore (it's looked up at runtime), hardcode the BDF value for the use of early serial. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 17:18:22 +08:00
#define X86_SOC_EARLY_SERIAL_PCIDEV PCIE_BDF(0, 0x18, 0) /* uart0 */
arch/x86: early_serial cleanup Various cleanups to the x86 early serial driver, mostly with the goal of simplifying its deployment during board bringup (which is really the only reason it exists in the first place): + Configure it =y by default. While there are surely constrained environments that will want to disable it, this is a TINY driver, and it serves a very important role for niche tasks. It should be built always to make sure it works everywhere. + Decouple from devicetree as much as possible. This code HAS to work during board bringup, often with configurations cribbed from other machines, before proper configuration gets written. Experimentally, devicetree errors tend to be easy to make, and without a working console impossible to diagnose. Specify the device via integer constants in soc.h (in the case of IOPORT access, we already had such a symbol) so that the path from what the developer intends to what the code executes is as short and obvious as possible. Unfortunately I'm not allowed to remove devicetree entirely here, but at least a developer adding a new platform will be able to override it in an obvious way instead of banging blindly on the other side of a DTS compiler. + Don't try to probe the PCI device by ID to "verify". While this sounds like a good idea, in practice it's just an extra thing to get wrong. If we bail on our early console because someone (yes, that's me) got the bus/device/function right but typoed the VID/DID numbers, we're doing no one any favors. + Remove the word-sized-I/O feature. This is a x86 driver for a PCI device. No known PC hardware requires that UART register access be done in dword units (in fact doing so would be a violation of the PCI specifciation as I understand it). It looks to have been cut and pasted from the ns16550 driver, remove. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-06-12 22:59:28 +08:00
arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
#endif /* __SOC_H_ */