zephyr/boards/riscv/m2gl025_miv/m2gl025_miv.yaml

identifier: m2gl025_miv
name: Microsemi M2GL025 with MiV target
type: mcu
arch: riscv32
toolchain:
  - zephyr
ram: 64
simulation: renode
testing:
  default: true
  ignore_tags:
    - net
    - bluetooth
riscv32: riscv-privilege: Microsemi Mi-V support This commit adds support for Microsemi Mi-V RISC-V softcore CPU running on the M2GL025 IGLOO2 FPGA development board. signed-off-by: Karol Gugala <kgugala@antmicro.com> 2018-06-11 01:02:14 +08:00			`identifier: m2gl025_miv`
			`name: Microsemi M2GL025 with MiV target`
			`type: mcu`
			`arch: riscv32`
			`toolchain:`
			`- zephyr`
			`ram: 64`
sanitycheck: Enable Renode tests on m2gl025_miv The test suite will use the m2gl025_miv.resc Renode script to load the platform. Signed-off-by: Dawid Wojciechowski <dwojciechowski@internships.antmicro.com> Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> 2019-01-07 23:42:54 +08:00			`simulation: renode`
riscv32: riscv-privilege: Microsemi Mi-V support This commit adds support for Microsemi Mi-V RISC-V softcore CPU running on the M2GL025 IGLOO2 FPGA development board. signed-off-by: Karol Gugala <kgugala@antmicro.com> 2018-06-11 01:02:14 +08:00			`testing:`
boards/riscv/m2gl025_miv: run tests on m2gl025_miv board by default Issue #37006 highlighted that some tests are prone to not passing on QEMU for 32-bit RISC-V. This commit enables running tests in Renode on emulated 32-bit RISC-V m2gl025_miv platform as a double-check. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com> 2021-08-06 20:06:18 +08:00			`default: true`
riscv32: riscv-privilege: Microsemi Mi-V support This commit adds support for Microsemi Mi-V RISC-V softcore CPU running on the M2GL025 IGLOO2 FPGA development board. signed-off-by: Karol Gugala <kgugala@antmicro.com> 2018-06-11 01:02:14 +08:00			`ignore_tags:`
			`- net`
			`- bluetooth`