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zephyr/dts/riscv/lowrisc/opentitan_earlgrey.dtsi

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boards: riscv: Add initial support for OpenTitan Earl Grey This board is confirmed to build and run simple applications in RTL simulation as described in the included board documentation. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:25:59 +08:00
/*
* Copyright (c) 2023 by Rivos Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "lowrisc,opentitan-earlgrey";
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
cpu@0 {
device_type = "cpu";
reg = <0x00>;
status = "okay";
dts/riscv/lowrisc: add `lowrisc,ibex` compatible string The OpenTitan Earlgrey SoC has the lowRISC Ibex CPU core. This commits adds the `lowrisc,ibex` compatible string to reflect that. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-01-18 17:27:01 +08:00
compatible = "lowrisc,ibex", "riscv";
dts/riscv: add missing `riscv,isa` fields and modify existing ones This commit adds/modifies `riscv,isa` strings using the following rules: * the ISA string is lowercase * multi-letter extensions are preceded with the underscore mark * if an extension is implied by another one, it is not specified - e.g. the D extension implies the F extension, so writing `rv32ifd` is redundant Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2023-09-05 21:15:25 +08:00
riscv,isa = "rv32imcb_zicsr_zifencei";
boards: riscv: Add initial support for OpenTitan Earl Grey This board is confirmed to build and run simple applications in RTL simulation as described in the included board documentation. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:25:59 +08:00
hlic: interrupt-controller {
#interrupt-cells = <0x01>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
};
soc {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "simple-bus";
ranges;
flash0: flash@20000000 {
reg = <0x20000000 0x100000>;
compatible = "soc-nv-flash";
};
ram0: memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x10000>;
};
mtimer: timer@40100000 {
compatible = "lowrisc,machine-timer";
reg = <0x40100000 0x200>;
interrupts = <7 0>;
interrupt-parent = <&hlic>;
status = "disabled";
};
boards: riscv: opentitan_earlgrey: Add the OpenTitan AON Timer Adds the AON Timer device in the OpenTitan Earlgrey device tree. Adds overlay files to enable the watchdog and set the alias to `watchdog0`. Adds the AON timer (watchdog part) to the supported features section of the OpenTitan documentation. Signed-off-by: Tyler Ng <tkng@rivosinc.com>
2023-04-26 04:46:06 +08:00
aontimer: aontimer@40470000 {
compatible = "lowrisc,opentitan-aontimer";
reg = <0x40470000 0x1000>;
interrupts = <156 1>;
interrupt-names = "wdog_bark";
interrupt-parent = <&plic>;
clock-frequency = <200000>;
status = "disabled";
};
dts: riscv: lowrisc: Add pwrmgr node to OpenTitan Earlgrey devicetree Adds the pwrmgr devicetree node. This is a simple binding that holds only the address of the registers for now. This patch is part of the OpenTitan watchdog (AON Timer) support patch series. It is needed to ensure that the watchdog reset functionality is enabled. Signed-off-by: Tyler Ng <tkng@rivosinc.com>
2023-05-10 06:34:49 +08:00
pwrmgr: pwrmgr@40400000 {
compatible = "lowrisc,opentitan-pwrmgr";
reg = <0x40400000 0x80>;
status = "okay";
};
boards: riscv: Add initial support for OpenTitan Earl Grey This board is confirmed to build and run simple applications in RTL simulation as described in the included board documentation. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:25:59 +08:00
plic: interrupt-controller@48000000 {
compatible = "sifive,plic-1.0.0";
#address-cells = <0>;
#interrupt-cells = <2>;
interrupt-controller;
interrupts-extended = <&hlic 11>;
drivers: intc: plic: define all registers' offset in the driver Define all the register offset directly in the driver according to the RISCV PLIC specification as they are not configurable, see: https://github.com/riscv/riscv-plic-spec. Updated devicetrees that has PLIC accordingly. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-09-21 15:40:10 +08:00
reg = <0x48000000 0x04000000>;
boards: riscv: Add initial support for OpenTitan Earl Grey This board is confirmed to build and run simple applications in RTL simulation as described in the included board documentation. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:25:59 +08:00
riscv,max-priority = <7>;
dts: opentitan: update plic interrupt count to match spec previously `184`, update to `182`, per: https://opentitan.org/book/hw/top_earlgrey/ip_autogen/rv_plic/ Signed-off-by: nagendra modadugu <ngm@meta.com>
2024-03-13 01:04:28 +08:00
riscv,ndev = <182>;
boards: riscv: opentitan_earlgrey: Add the OpenTitan AON Timer Adds the AON Timer device in the OpenTitan Earlgrey device tree. Adds overlay files to enable the watchdog and set the alias to `watchdog0`. Adds the AON timer (watchdog part) to the supported features section of the OpenTitan documentation. Signed-off-by: Tyler Ng <tkng@rivosinc.com>
2023-04-26 04:46:06 +08:00
status = "okay";
boards: riscv: Add initial support for OpenTitan Earl Grey This board is confirmed to build and run simple applications in RTL simulation as described in the included board documentation. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:25:59 +08:00
};
uart0: serial@40000000{
reg = <0x40000000 0x1000>;
compatible = "lowrisc,opentitan-uart";
status = "disabled";
};
boards: riscv: opentitan_earlgrey: Add SPI host peripherals Add 2x SPI host peripherals. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-02-09 07:50:48 +08:00
spi0: spi@40300000 {
compatible = "lowrisc,opentitan-spi";
status = "disabled";
reg = <0x40300000 0x100>;
clock-frequency = <96000000>;
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@40310000 {
compatible = "lowrisc,opentitan-spi";
status = "disabled";
reg = <0x40310000 0x100>;
clock-frequency = <48000000>;
#address-cells = <1>;
#size-cells = <0>;
};
boards: riscv: Add initial support for OpenTitan Earl Grey This board is confirmed to build and run simple applications in RTL simulation as described in the included board documentation. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:25:59 +08:00
};
};