49 lines
902 B
Plaintext
49 lines
902 B
Plaintext
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/*
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* Copyright (c) 2023 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx3";
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reg = <0>;
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};
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};
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/*
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* Although RAM is of size 128MB (0x08000000), limit this to 16MB so
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* fewer L2 page table entries are needed when MMU is enabled.
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*/
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sram0: memory@00000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x00000000 0x01000000>;
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};
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/*
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* Although ROM is of size 32MB (0x02000000), limit this to 8KB so
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* fewer L2 page table entries are needed when MMU is enabled.
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*/
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rom0: memory@fe000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xfe000000 0x00002000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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};
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};
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