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zephyr/dts/x86/apollo_lake.dtsi

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arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
/*
gpio: intel_apl: rework driver for pin_mask callback To avoid confusion, callbacks using ordinal pin numbers is going to be reverted. So the driver has to be re-worked to expose multiple devices so each device has 32 pins. Also fixes #12765 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-01-30 11:34:41 +08:00
* Copyright (c) 2017-2019 Intel Corporation.
arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/intel-ioapic.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "apollo_lake";
reg = <0>;
};
intc: ioapic@fec00000 {
compatible = "intel,ioapic";
reg = <0xfec00000 0x100000>;
interrupt-controller;
#interrupt-cells = <3>;
};
};
flash0: flash@100000{
dts: Add missing 'compatible' property in flash base nodes 'compatible' property was missing in flash base nodes for some .dtsi files. Fix this. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-09-21 07:39:55 +08:00
compatible = "soc-nv-flash";
arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
reg = <0x00100000 DT_FLASH_SIZE>;
};
sram0: memory@400000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x00400000 DT_SRAM_SIZE>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
gpio: add driver for Intel Apollo Lake SoC This adds a driver for GPIO controller on the Intel Apollo Lake SoC. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-09-20 01:15:12 +08:00
dts: x86: Fix dts warnings when building up_squared Fix the following dts warnings: up_squared.dts_compiled: Warning (simple_bus_reg): /soc/gpio@0: simple-bus unit address format error, expected "d0c50000" up_squared.dts_compiled: Warning (simple_bus_reg): /soc/i2c@91528000: simple-bus unit address format error, expected "9158000" Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-10-18 11:24:26 +08:00
gpio: gpio@d0c50000 {
gpio: add driver for Intel Apollo Lake SoC This adds a driver for GPIO controller on the Intel Apollo Lake SoC. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-09-20 01:15:12 +08:00
compatible = "intel,apl-gpio";
reg = <0xd0c50000 0x1000>,
<0xd0c40000 0x1000>,
<0xd0c70000 0x1000>,
<0xd0c00000 0x1000>;
gpio: intel_apl: rework driver for pin_mask callback To avoid confusion, callbacks using ordinal pin numbers is going to be reverted. So the driver has to be re-worked to expose multiple devices so each device has 32 pins. Also fixes #12765 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-01-30 11:34:41 +08:00
label = "APL_GPIO";
gpio: add driver for Intel Apollo Lake SoC This adds a driver for GPIO controller on the Intel Apollo Lake SoC. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-09-20 01:15:12 +08:00
gpio-controller ;
#gpio-cells = <2>;
status = "disabled";
};
arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
};
gpio: intel_apl: rework driver for pin_mask callback To avoid confusion, callbacks using ordinal pin numbers is going to be reverted. So the driver has to be re-worked to expose multiple devices so each device has 32 pins. Also fixes #12765 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-01-30 11:34:41 +08:00
sharedirq0: sharedirq0 {
compatible = "shared-irq";
label = "APL_GPIO_IRQ";
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "ok";
};
arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
};