2017-09-08 02:07:36 +08:00
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/dts-v1/;
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2018-09-15 12:21:56 +08:00
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#include <mem.h>
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#define DT_FLASH_SIZE DT_SIZE_K(4092)
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2017-11-07 01:32:33 +08:00
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#if XIP
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2018-09-15 12:21:56 +08:00
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#define DT_SRAM_SIZE DT_SIZE_K(4096)
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2017-11-07 01:32:33 +08:00
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#else
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2018-09-15 12:21:56 +08:00
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#define DT_SRAM_SIZE DT_SIZE_K(8188)
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2017-11-07 01:32:33 +08:00
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#endif
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2017-09-08 02:07:36 +08:00
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#include <ia32.dtsi>
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/ {
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model = "QEMU X86";
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compatible = "intel,ia32";
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aliases {
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2018-04-11 00:56:14 +08:00
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uart-0 = &uart0;
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uart-1 = &uart1;
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2017-09-08 02:07:36 +08:00
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};
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,console = &uart0;
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2018-11-27 19:11:04 +08:00
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zephyr,shell-uart = &uart0;
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2017-09-08 02:07:36 +08:00
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zephyr,bt-uart = &uart1;
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zephyr,uart-pipe = &uart1;
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zephyr,bt-mon-uart = &uart1;
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};
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2018-07-31 16:35:20 +08:00
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soc {
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eth0: eth@febc0000 {
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compatible = "intel,e1000";
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reg = <0xfebc0000 0x100>;
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label = "eth0";
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interrupts = <11 IRQ_TYPE_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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status = "ok";
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};
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};
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2017-09-08 02:07:36 +08:00
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};
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&uart0 {
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status = "ok";
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current-speed = <115200>;
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};
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&uart1 {
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status = "ok";
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current-speed = <115200>;
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};
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