zephyr/dts/bindings/cpu/telink,b91.yaml

# Copyright (c) 2021 Telink Semiconductor
# SPDX-License-Identifier: Apache-2.0

description: Telink RISC-V CPU

compatible: "telink,b91"

include: riscv,cpus.yaml
dts: riscv: add basic dts support for new Telink B91 platform CPU, Power, GPIO, Serial and Pinctrl dtsi support for new Telink B91 RISC-V platform. Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com> 2021-07-09 16:40:02 +08:00			`# Copyright (c) 2021 Telink Semiconductor`
			`# SPDX-License-Identifier: Apache-2.0`

			`description: Telink RISC-V CPU`

			`compatible: "telink,b91"`

dts/riscv: add missing `riscv,isa` fields and modify existing ones This commit adds/modifies `riscv,isa` strings using the following rules: * the ISA string is lowercase * multi-letter extensions are preceded with the underscore mark * if an extension is implied by another one, it is not specified - e.g. the D extension implies the F extension, so writing `rv32ifd` is redundant Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com> 2023-09-05 21:15:25 +08:00			`include: riscv,cpus.yaml`