zephyr/dts/bindings/cpu/intel,niosv.yaml

# Copyright (C) 2023, Intel Corporation
# SPDX-License-Identifier: Apache-2.0

description: INTEL FPGA NIOSV Softcore Processor

compatible: "intel,niosv"

include: riscv,cpus.yaml
dts: bindings: cpu: Add INTEL FPGA NIOSV Add INTEL FPGA NIOSV Processor yaml file Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com> 2023-02-03 15:04:49 +08:00			`# Copyright (C) 2023, Intel Corporation`
			`# SPDX-License-Identifier: Apache-2.0`

			`description: INTEL FPGA NIOSV Softcore Processor`

			`compatible: "intel,niosv"`

dts/riscv: add missing `riscv,isa` fields and modify existing ones This commit adds/modifies `riscv,isa` strings using the following rules: * the ISA string is lowercase * multi-letter extensions are preceded with the underscore mark * if an extension is implied by another one, it is not specified - e.g. the D extension implies the F extension, so writing `rv32ifd` is redundant Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com> 2023-09-05 21:15:25 +08:00			`include: riscv,cpus.yaml`