2015-04-11 07:44:37 +08:00
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/*
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* Copyright (c) 2013-2014, Wind River Systems, Inc.
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*
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2017-01-19 09:01:01 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2015-04-11 07:44:37 +08:00
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*/
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/*
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2015-10-21 00:42:33 +08:00
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* DESCRIPTION
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* Platform independent, commonly used macros and defines related to linker
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* script.
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*
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* This file may be included by:
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* - Linker script files: for linker section declarations
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* - C files: for external declaration of address or size of linker section
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* - Assembly files: for external declaration of address or size of linker
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* section
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2015-07-02 05:22:39 +08:00
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*/
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2015-04-11 07:44:37 +08:00
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#ifndef _LINKERDEFS_H
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#define _LINKERDEFS_H
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#include <toolchain.h>
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#include <sections.h>
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/* include platform dependent linker-defs */
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2015-10-09 18:20:52 +08:00
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#ifdef CONFIG_X86
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2016-10-22 00:29:09 +08:00
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/* Nothing yet to include */
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2015-06-06 10:27:08 +08:00
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#elif defined(CONFIG_ARM)
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2015-04-11 07:44:37 +08:00
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/* Nothing yet to include */
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2015-06-06 10:27:49 +08:00
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#elif defined(CONFIG_ARC)
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2015-04-11 07:44:37 +08:00
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/* Nothing yet to include */
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2016-04-22 05:47:09 +08:00
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#elif defined(CONFIG_NIOS2)
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/* Nothing yet to include */
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arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 07:24:30 +08:00
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#elif defined(CONFIG_RISCV32)
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/* Nothing yet to include */
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2017-01-26 05:26:58 +08:00
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#elif defined(CONFIG_XTENSA)
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/* Nothing yet to include */
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2015-04-11 07:44:37 +08:00
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#else
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#error Arch not supported.
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#endif
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#ifdef _LINKER
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2015-10-14 23:17:20 +08:00
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2016-04-09 03:38:57 +08:00
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/*
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* Space for storing per device busy bitmap. Since we do not know beforehand
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* the number of devices, we go through the below mechanism to allocate the
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* required space.
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*/
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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2016-11-08 23:36:50 +08:00
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#define DEVICE_COUNT \
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((__device_init_end - __device_init_start) / _DEVICE_STRUCT_SIZE)
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2016-04-09 03:38:57 +08:00
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#define DEV_BUSY_SZ (((DEVICE_COUNT + 31) / 32) * 4)
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#define DEVICE_BUSY_BITFIELD() \
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FILL(0x00) ; \
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__device_busy_start = .; \
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. = . + DEV_BUSY_SZ; \
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__device_busy_end = .;
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#else
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#define DEVICE_BUSY_BITFIELD()
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#endif
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2015-10-14 23:17:20 +08:00
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/*
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* generate a symbol to mark the start of the device initialization objects for
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* the specified level, then link all of those objects (sorted by priority);
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* ensure the objects aren't discarded if there is no direct reference to them
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*/
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#define DEVICE_INIT_LEVEL(level) \
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__device_##level##_start = .; \
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KEEP(*(SORT(.init_##level[0-9]))); \
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KEEP(*(SORT(.init_##level[1-9][0-9]))); \
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/*
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* link in device initialization objects for all devices that are automatically
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* initialized by the kernel; the objects are sorted in the order they will be
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* initialized (i.e. ordered by level, sorted by priority within a level)
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*/
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#define DEVICE_INIT_SECTIONS() \
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2016-11-09 03:06:55 +08:00
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__device_init_start = .; \
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DEVICE_INIT_LEVEL(PRE_KERNEL_1) \
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DEVICE_INIT_LEVEL(PRE_KERNEL_2) \
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DEVICE_INIT_LEVEL(POST_KERNEL) \
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DEVICE_INIT_LEVEL(APPLICATION) \
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2016-04-09 03:38:57 +08:00
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__device_init_end = .; \
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DEVICE_BUSY_BITFIELD() \
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2015-10-14 23:17:20 +08:00
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2015-10-27 03:40:46 +08:00
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/* define a section for undefined device initialization levels */
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#define DEVICE_INIT_UNDEFINED_SECTION() \
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KEEP(*(SORT(.init_[_A-Z0-9]*))) \
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2016-07-31 21:16:29 +08:00
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/*
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* link in shell initialization objects for all modules that use shell and
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* their shell commands are automatically initialized by the kernel.
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*/
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#define SHELL_INIT_SECTIONS() \
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__shell_cmd_start = .; \
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KEEP(*(".shell_*")); \
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__shell_cmd_end = .;
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2015-10-09 18:20:52 +08:00
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#ifdef CONFIG_X86 /* LINKER FILES: defines used by linker script */
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2015-04-11 07:44:37 +08:00
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/* Should be moved to linker-common-defs.h */
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#if defined(CONFIG_XIP)
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#define ROMABLE_REGION ROM
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#else
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#define ROMABLE_REGION RAM
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#endif
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#endif
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/*
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* If image is loaded via kexec Linux system call, then program
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* headers need to be page aligned.
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* This can be done by section page aligning.
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*/
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#ifdef CONFIG_BOOTLOADER_KEXEC
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#define KEXEC_PGALIGN_PAD(x) . = ALIGN(x);
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#else
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#define KEXEC_PGALIGN_PAD(x)
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#endif
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#elif defined(_ASMLANGUAGE)
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2015-10-14 23:17:20 +08:00
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2015-04-11 07:44:37 +08:00
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/* Assembly FILES: declaration defined by the linker script */
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GDATA(__bss_start)
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GDATA(__bss_num_words)
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#ifdef CONFIG_XIP
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GDATA(__data_rom_start)
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GDATA(__data_ram_start)
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GDATA(__data_num_words)
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#endif
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2015-10-14 23:17:20 +08:00
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#else /* ! _ASMLANGUAGE */
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2015-04-11 07:44:37 +08:00
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Introduce new sized integer typedefs
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t. This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.
We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.
We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.
Jira: ZEP-2051
Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-19 23:32:08 +08:00
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#include <zephyr/types.h>
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2015-04-11 07:44:37 +08:00
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extern char __bss_start[];
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2016-07-01 07:45:08 +08:00
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extern char __bss_end[];
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2015-04-11 07:44:37 +08:00
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#ifdef CONFIG_XIP
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extern char __data_rom_start[];
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extern char __data_ram_start[];
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2016-07-01 07:45:08 +08:00
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extern char __data_ram_end[];
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2015-04-11 07:44:37 +08:00
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#endif
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2015-09-17 07:14:40 +08:00
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extern char _image_rom_start[];
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extern char _image_rom_end[];
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extern char _image_ram_start[];
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extern char _image_ram_end[];
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2015-09-22 05:57:39 +08:00
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extern char _image_text_start[];
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extern char _image_text_end[];
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2015-09-17 07:14:40 +08:00
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2015-04-11 07:44:37 +08:00
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/* end address of image. */
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extern char _end[];
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#endif /* ! _ASMLANGUAGE */
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#endif /* _LINKERDEFS_H */
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