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zephyr/boards/riscv32/qemu_riscv32/qemu_riscv32_defconfig

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boards: added support for the qemu_riscv32 board The qemu_riscv32 board makes use of: 1) the uart_riscv_qemu driver 2) the riscv_qemu_timer driver Change-Id: I413e3990a66bc62a0d15d82ebca6940b381fed43 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 07:24:31 +08:00
CONFIG_RISCV32=y
qemu_riscv32: use hifive1 configuration Use hifive1 configuration for this qemu and set SYS_CLOCK_HW_CYCLES_PER_SEC to 10000000 Fixes #10043 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-14 22:37:38 +08:00
CONFIG_SOC_SERIES_RISCV32_SIFIVE_FREEDOM=y
CONFIG_SOC_RISCV32_SIFIVE_FREEDOM=y
boards: added support for the qemu_riscv32 board The qemu_riscv32 board makes use of: 1) the uart_riscv_qemu driver 2) the riscv_qemu_timer driver Change-Id: I413e3990a66bc62a0d15d82ebca6940b381fed43 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 07:24:31 +08:00
CONFIG_BOARD_QEMU_RISCV32=y
CONFIG_CONSOLE=y
CONFIG_PRINTK=y
CONFIG_SERIAL=y
qemu_riscv32: use hifive1 configuration Use hifive1 configuration for this qemu and set SYS_CLOCK_HW_CYCLES_PER_SEC to 10000000 Fixes #10043 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-14 22:37:38 +08:00
CONFIG_UART_SIFIVE=y
CONFIG_UART_SIFIVE_PORT_0=y
boards: added support for the qemu_riscv32 board The qemu_riscv32 board makes use of: 1) the uart_riscv_qemu driver 2) the riscv_qemu_timer driver Change-Id: I413e3990a66bc62a0d15d82ebca6940b381fed43 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 07:24:31 +08:00
CONFIG_UART_CONSOLE=y
qemu_riscv32: use hifive1 configuration Use hifive1 configuration for this qemu and set SYS_CLOCK_HW_CYCLES_PER_SEC to 10000000 Fixes #10043 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-14 22:37:38 +08:00
CONFIG_PLIC=y
CONFIG_PINMUX=y
CONFIG_PINMUX_SIFIVE=y
riscv32: timer: replace riscv_qemu_driver by the generic riscv_machine_driver riscv defines the machine-mode timer registers that are implemented by the all riscv SOCs that follow the riscv privileged architecture specification. The timer registers implemented in riscv-qemu follow this specification. To account for future riscv SOCs, reimplement the riscv_qemu_driver by the riscv_machine_driver. Change-Id: I645b03c91b4e07d0f2609908decc27ba9b8240d4 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-24 08:03:56 +08:00
CONFIG_RISCV_MACHINE_TIMER=y
qemu_riscv32: use hifive1 configuration Use hifive1 configuration for this qemu and set SYS_CLOCK_HW_CYCLES_PER_SEC to 10000000 Fixes #10043 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-14 22:37:38 +08:00
CONFIG_GPIO=y
CONFIG_GPIO_SIFIVE=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000