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zephyr/boards/xtensa/intel_s1000_crb/Kconfig.defconfig

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intel_s1000: add intel_s1000_crb board intel_s1000_crb board makes use of the intel_s1000 SoC. It has a built-in ROM which gets executed upon applying power. It then executes the secondary bootloader followed by the FW (like zephyr). Change-Id: If334c359b4372a56997c3b2e1eb9250e80847f07 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-23 13:57:25 +08:00
# Copyright (c) 2017 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
if BOARD_INTEL_S1000_CRB
config BOARD
default intel_s1000_crb
config BOARD_XTENSA
def_bool y
xtensa: intel_s1000: implement interrupt mechanism intel_s1000 has multiple levels of interrupts consisting of core, CAVS Logic and designware interrupt controller. This patchset modifies the regular gen_isr mechanism to support these multiple levels. Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-12 21:02:23 +08:00
config CAVS_ICTL_0_OFFSET
default 0x06
config CAVS_ICTL_1_OFFSET
default 0x0A
config CAVS_ICTL_2_OFFSET
default 0x0D
config CAVS_ICTL_3_OFFSET
default 0x10
config DW_ICTL_OFFSET
default 0x07
config 2ND_LVL_INTR_00_OFFSET
default CAVS_ICTL_0_OFFSET
config 2ND_LVL_INTR_01_OFFSET
default CAVS_ICTL_1_OFFSET
config 2ND_LVL_INTR_02_OFFSET
default CAVS_ICTL_2_OFFSET
config 2ND_LVL_INTR_03_OFFSET
default CAVS_ICTL_3_OFFSET
config 3RD_LVL_INTR_00_OFFSET
default DW_ICTL_OFFSET
config MAX_IRQ_PER_AGGREGATOR
default 32
config NUM_2ND_LEVEL_AGGREGATORS
default 4
config NUM_3RD_LEVEL_AGGREGATORS
default 1
config 2ND_LVL_ISR_TBL_OFFSET
default 21
config 3RD_LVL_ISR_TBL_OFFSET
default 149
config CAVS_ISR_TBL_OFFSET
default 2ND_LVL_ISR_TBL_OFFSET
config DW_ISR_TBL_OFFSET
default 3RD_LVL_ISR_TBL_OFFSET
intel_s1000: gpio: enable GPIO handling Enable GPIO handling for intel_s1000. It uses a DesignWare IP. Change-Id: I522534935e4ef3a56d93aca669f6de961d927481 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-08 11:14:24 +08:00
config GPIO_DW_0_NAME
default "GPIO_PORTA"
config GPIO_DW_0_IRQ_PRI
default 1
intel_s1000: i2c: enable I2C for intel_s1000 intel_s1000 makes use of DesignWare IP for I2C. Change-Id: Ie091318c5959b95e1febeb5cefa440f35a6d144b Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-11 14:30:05 +08:00
config I2C_0_DEFAULT_CFG
default 0x12
config I2C_0_IRQ_PRI
default 0
intel_s1000: uart: configure UART for intel_s1000 intel_s1000 uses DesignWare IP for UART. National Semiconductor 16550 (UART) component specification is followed in this IP. Change-Id: Ied7df1dc178d55b6dbe71d729d6383ba07274ea4 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-08-30 17:15:44 +08:00
if UART_NS16550
config UART_NS16550_PORT_0
def_bool y
if UART_NS16550_PORT_0
config UART_NS16550_PORT_0_NAME
default "UART_0"
config UART_NS16550_PORT_0_BAUD_RATE
default 115200
config UART_NS16550_PORT_0_OPTIONS
default 0
xtensa: intel_s1000: implement interrupt mechanism intel_s1000 has multiple levels of interrupts consisting of core, CAVS Logic and designware interrupt controller. This patchset modifies the regular gen_isr mechanism to support these multiple levels. Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-12 21:02:23 +08:00
config UART_INTERRUPT_DRIVEN
def_bool y
intel_s1000: uart: configure UART for intel_s1000 intel_s1000 uses DesignWare IP for UART. National Semiconductor 16550 (UART) component specification is followed in this IP. Change-Id: Ied7df1dc178d55b6dbe71d729d6383ba07274ea4 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-08-30 17:15:44 +08:00
endif # UART_NS16550_PORT_0
endif # UART_NS16550
intel_s1000: add intel_s1000_crb board intel_s1000_crb board makes use of the intel_s1000 SoC. It has a built-in ROM which gets executed upon applying power. It then executes the secondary bootloader followed by the FW (like zephyr). Change-Id: If334c359b4372a56997c3b2e1eb9250e80847f07 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-23 13:57:25 +08:00
endif # BOARD_INTEL_S1000_CRB