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zephyr/soc/nordic/common/vpr/soc_context.h

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soc: riscv: nordic_nrf: add initial support for VPR core Add initial support for the VPR RISC-V core found in the new nRF54 SoCs. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-02-01 02:46:00 +08:00
/*
* Copyright (C) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef SOC_RISCV_NORDIC_NRF_COMMON_VPR_SOC_CONTEXT_H_
#define SOC_RISCV_NORDIC_NRF_COMMON_VPR_SOC_CONTEXT_H_
soc: nordic: vpr: fix soc isr sw stacking. Fixed order of mepc and _mcause in esf for 32bit stacking. Added missing stack pointer alignement bit support.' Signed-off-by: Lukasz Stepnicki <lukasz.stepnicki@nordicsemi.no>
2024-04-18 19:16:32 +08:00
#define SOC_ESF_MEMBERS \
unsigned long minttresh; \
unsigned long sp_align; \
unsigned long padding0; \
unsigned long padding1; \
unsigned long padding2
#define SOC_ESF_INIT \
0, \
0, \
0, \
0
soc: riscv: nordic_nrf: add initial support for VPR core Add initial support for the VPR RISC-V core found in the new nRF54 SoCs. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-02-01 02:46:00 +08:00
#endif /* SOC_RISCV_NORDIC_NRF_COMMON_VPR_SOC_CONTEXT_H_ */